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performance motion devices, inc. 55 old bedford road lincoln, ma 01773 pilot? motion processor MC3310 single chip technical specifications for brushless servo motion control revision 1.7, july 2003
notice this document contains proprietary and confidential information of performance motion devices, inc., and is protected by federal co pyright law. the contents of this document may not be disclosed to third parties, translated, copied, or duplicated in any form, in whole or in part, without the express written permission of pmd. the information contained in this document is subject to change without notice. no part of this document may be reproduced or transmitted in an y form, by any means, electronic or mechanical, for any purpose, without the express written permission of pmd. copyright 2000 by performance motion devices, inc. navigator, pilot and c-motion are trademarks of performance motion devices, inc
MC3310 technical specifications iii warranty pmd warrants performance of its products to the specifications applicable at the time of sale in accordance with pmd's standard wa rranty. testing and other quality control techniques are utilized to the extent pmd deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. performance motion devices, inc. (pmd) reserves th e right to make changes to its products or to discontinue any product or service without notice, and advises customers to obtain the latest version of relevant information to verify, before placin g orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. safety notice certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage. products are not designed, authorized, or warranted to be suitable for use in life support devices or systems or other critical applications. inclusion of pmd products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the cust omer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent procedural hazards. disclaimer pmd assumes no liability for applic ations assistance or cu stomer product design. pmd does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual pr operty right of pmd covering or relating to any combination, machine, or process in which such prod ucts or services might be or are used. pmd's publication of information regarding any third party's products or services does not constitute pmd's approval, warranty or endorsement thereof.
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MC3310 technical specifications v related documents pilot motion processor user?s guide (mc3000ug) how to set up and use all members of the pilot motion processor family. pilot motion processor progra mmer?s reference (mc3000pr) descriptions of all pilot motion processor commands, with coding syntax and examples, listed alphabetically for quick reference. pilot motion processor t echnical specifications these booklets contain physical and electrical characteristics, timing diagrams, pinouts and pin descriptions of each: mc3110, for brushed servo motion control (mc3110ts) MC3310, for brushless servo motion control (MC3310ts) mc3410, for microsteppi ng motion control (mc3410ts) mc3510, for stepper motion control (mc3510ts) pilot motion processor developer?s kit manual (dk3000m) how to install and configure the dk3310 developer?s kit pc board.
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MC3310 technical specifications vii table of contents warranty....................................................................................................................... ............................... iii safety notice .................................................................................................................. .............................. iii discla imer..................................................................................................................... ................................ iii related do cuments.............................................................................................................. ......................... v table of contents.............................................................................................................. .......................... vii 1 the pilo t fam ily ............................................................................................................. ........................... 9 2 functional characteristics................................................................................................... ................... 11 2.1 configurations, paramete rs, and performance .............................................................................. 11 2.2 physical characteristics and mounting dimensions....................................................................... 13 2.3 environmental and electrical ratings ........................................................................................... .14 2.4 system configuration........................................................................................................... ......... 14 2.5 peripheral device address mapping.............................................................................................. .15 3 electrical char acteristics................................................................................................... ..................... 16 3.1 dc charact eristic s............................................................................................................. ............ 16 3.2 ac charact eristic s............................................................................................................. ............ 16 4 i/o timing diagrams .......................................................................................................... .................... 18 4.1 clock .......................................................................................................................... .................. 18 4.2 quadrature encoder input ....................................................................................................... ...... 18 4.3 reset .......................................................................................................................... ................... 18 4.4 host interface, 8/16 mode (requ ires external logic device) .......................................................... 19 4.4.1 instruction write, 8/16 mode................................................................................................. 19 4.4.2 data write, 8/16 mode.......................................................................................................... .19 4.4.3 data read, 8/16 mode........................................................................................................... .20 4.4.4 status read, 8/16 mode......................................................................................................... .20 4.5 host interface, 16/16 mode (re quires external logic device) ........................................................ 21 4.5.1 instruction write, 16/16 mode............................................................................................... 21 4.5.2 data write, 16/16 mode......................................................................................................... 21 4.5.3 data read, 16/16 mode.......................................................................................................... 22 4.5.4 status read, 16/16 mode........................................................................................................ 22 4.6 external memory timing......................................................................................................... ...... 23 4.6.1 external memory read........................................................................................................... 23 4.6.2 external memo ry write ......................................................................................................... 2 3 4.7 peripheral device timing ....................................................................................................... ........ 24 4.7.1 peripheral device read......................................................................................................... .. 24 4.7.2 peripheral device write ........................................................................................................ .24 5 pinouts and pi n descriptions................................................................................................. ................. 25 5.1 pinouts fo r MC3310 ............................................................................................................. ........ 25 5.2 cp chip pin description table.................................................................................................. ...... 26
MC3310 technical specifications viii 6 parallel co mmunica tion ....................................................................................................... .................. 30 6.1 host interface pin de scription table ........................................................................................... ... 30 6.2 16-bit host inte rface (iopil16) ................................................................................................ ... 32 6.3 8-bit host inte rface (iopil8) .................................................................................................. ..... 46 7 applicatio n notes............................................................................................................ ......................... 62 7.1 design tips.................................................................................................................... ............... 62 7.2 rs-232 serial interface ........................................................................................................ ........ 64 7.3 rs 422/485 seri al interface.................................................................................................... ...... 66 7.4 pwm motor interface ............................................................................................................ ...... 68 7.5 12-bit parallel dac interface.................................................................................................. ..... 70 7.6 16-bit serial dac interface.................................................................................................... ...... 72 7.7 ram inte rface.................................................................................................................. ............ 74 7.8 user-defined i/o ............................................................................................................... ............ 76 7.9 12-bit a/d interface........................................................................................................... ........... 78 7.10 16-bit a/d input ............................................................................................................... ............ 80 7.11 external gating logic index .................................................................................................... .... 82
MC3310 technical specifications 9 1 the pilot family mc3110 MC3310 mc3410 mc3510 number of axes 1 1 1 1 motor type supported brushed servo brushless servo stepping stepping output format brushed servo (single phase) commutated (6- step or sinusoidal) microstepping pulse and direction incremental encoder input parallel word device input parallel communication 1 1 1 1 serial communication s-curve profiling on-the-fly changes directional limit switches programmable bit output software-invertable signals pid servo control - - feedforward (accel & vel) - - derivative sampling time - - data trace/diagnostics pwm output - pulse & direction output - - - index & home signals motion error detection (with encoder) (with encoder) axis settled indicator (with encoder) (with encoder) dac-compatible output - position capture analog input user-defined i/o external ram support multi-chip synchronization (mc3113) (mc3313) (mc3413) - chip part numbers mc3110 MC3310 mc3410 mc3510 developer's kit p/n's: dk3110 dk3310 dk3410 dk3510 1 parallel communication is availa ble via an additional logic device introduction this manual describes the operational characteri stics of the MC3310 motion processor from pmd. this device is a member of the mc3000 family of single-chip, single-axis motion processors.
MC3310 technical specifications 10 each device of the mc3000 family is a complete chip-based motion processor providing trajectory generation and related motion control functions for one axis including servo loop closure or on- board commutation where appropriate. this family of products provides a software-compatible selection of dedicated motion processors that can handle a large variety of system configurations. the chip architecture not only makes it ideal for the task of motion control, it allows for similarities in software commands, so software written for one motor type can be re-used if the motor type is changed. pilot family summary mc3110 ? this single-chip, single-axis motion processor outputs motor commands in either sign/magnitude pwm or dac-compatible format for use with brushed servo motors, or with brushless servo motors having external commutation. MC3310 ? this single-chip, single-axis motion processor outputs sinusoidally commutated motor signals appropriate for driving brushless motors. depending on the motor type, the output is a two- phase or three-phase signal in either pwm or dac-compatible format. mc3410 ? this single-chip, single-axis motion processor outputs microstepping signals for stepping motors. two phased signals per axis are gene rated in either pwm or dac-compatible format. mc3510 ? this single-chip, single-axis motion processor outputs pulse and direction signals for stepping motor systems.
MC3310 technical specifications 11 2 functional characteristics 2.1 configurations, parameters, and performance configuration single axis, single chip. operating modes closed loop (motor command is driven from output of servo filter) open loop (motor command is driven from user-programmed register) communication modes 8/16 parallel (8 bit external parallel bus with 16 bit internal command word size) 16/16 parallel (16 bit external parallel bus with 16 bit internal command word size) point to point asynchronous serial multi-drop asynchronous serial serial port baud rate range 1,200 baud to 416,667 baud position range -2,147,483,648 to +2,147,483,647 counts velocity range -32,768 to +32,767 counts/sample with a resolution of 1/65,536 counts/sample acceleration/deceleration ranges -32,768 to +32,767 counts/sample 2 with a resolution of 1/65,536 counts/sample 2 jerk range 0 to ? counts/sample 3 , with a resolution of 1/4,294,967,296 counts/sample 3 profile modes s-curve point-to-point (velocity, acceleration, jerk, and position parameters) trapezoidal point-to-point (velocity, a cceleration, deceleration, and position parameters) velocity-contouring (velocity, acceleration, and deceleration parameters) filter modes scalable pid + velocity feedforward + acceleration feedforward + bias. also includes integration limit, settable derivative sampling time, and output motor command limiting filter parameter resolution 16 bits position error tracking motion error window (allows axis to be stopped upon exceeding programmable window) tracking window (allows flag to be set if axis exceeds a programmable position window) axis settled (allows flag to be set if axis exceeds a programmable position window for a programmable amount of time after trajectory motion is compete) motor output modes pwm (9-bit resolution at 20 khz) dac (16 bits) commutation rate 20 khz maximum encoder rate incremental (up to 5 million counts/sec) parallel-word (up to 160 million counts/sec) parallel encoder word size 16 bits parallel encoder read rate 20 khz (reads all axes every 50 sec) servo loop timing range 153.6 sec to 32.767 milliseconds minimum servo loop time 153.6 sec multi-chip synchronization <10 sec difference between master and slave servo cycle mc3313 chipset only limit switches 2 per axis: one for each direction of travel position-capture triggers 2 per axis: index and home signals
MC3310 technical specifications 12 other digital signals (per axis) 1 axisin signal per axis, 1 axisout signal per axis software-invertable signals index, home, axisin, axisout, positive limit, negativelimit (all individually programmable) analog input 8 10-bit analog inputs user defined discrete i/o 256 16-bit wide user defined i/o ram/external memory support 65,536 blocks of 32,768 16-bit words per block. total accessible memory is 2,147,483,648 16 bit words trace modes one-time continuous max. number of trace variables 4 number of traceable variables 28 number of host instructions 152
MC3310 technical specifications 13 2.2 physical characteristics and mounting dimensions all dimensions are in inches (with millimeters in brackets). dimension minimum (inches) maximum (inches) d 1.070 1.090 d1 0.934 0.966 d2 1.088 1.112 d3 0.800 nominal
MC3310 technical specifications 14 2.3 environmental and electrical ratings storage temperature (t s ) -55 c to 150 c operating temperature (t a ) 0 c to 70 c* power dissipation (p d ) 400 mw nominal clock frequency (f clk ) 20.0 mhz supply voltage limits (v cc ) -0.3v to +7.0v supply voltage operating range (v cc ) 4.75v to 5.25v * an industrial version with an operating range of -40 c to 85 c is also available. please contact pmd for more information. 2.4 system configuration the following figure shows the principal co ntrol and data paths in an MC3310 system. host cp hostdata0-15 ~hostslct parallel port serial port system clock (40 mhz) hostintrpt hostrdy ~hostwrite hostcmd ~hostread parallel-word input external memory user i/o serial port configuration parallel communication pld/fpga 2 0 m h z c l o c k 16 bit data/address bus axisout negative positive axisin hall sensors (MC3310 only) motor amplifier pwm output dac output d/a converter a home index b encoder pilot motion processor limit switches the shaded area shows the cpld /fpga that must be provided by the designer if parallel communication is required. a description and the n ecessary logic (in the form of schematics) of this device are detailed in section 6 of this manual. the cp chip contains the profile generator, which calculates velocity, acceleration, and position values for a trajectory; and the digital servo filter, which stabilizes the motor output signal.
MC3310 technical specifications 15 the filter produces one of two types of output: ? a pulse-width modulated (pwm) signal output; or ? a dac-compatible value routed via the d ata bus to the appropriate d/a converter. axis position information returns to the motion processor in the form of encoder feedback using either the incremental encoder input signals, or via the bus as parallel word input. 2.5 peripheral device address mapping device addresses on the cp chip?s data bus are memory-mapped to the following locations: address device description 0200h serial port data contains the configuration data (transmission rate, parity, stop bits, etc) for the asynchronous serial port 0800h parallel-word encoder base addre ss for parallel-word feedback devices 1000h user-defined base address for user-defined i/o devices 2000h ram page pointer page po inter to external memory 4000h motor-output dacs base addre ss for motor-output d/a converters 8000h parallel interface base address for parallel interface communication
MC3310 technical specifications 16 3 electrical characteristics 3.1 dc characteristics (v cc and t a per operating ratings, f clk = 20.0 mhz) symbol parameter minimum maximum conditions v cc supply voltage 4.75 v 5.25 v i dd supply current 80 ma open outputs input voltages v ih logic 1 input voltage 2.0 v v cc + 0.3 v v il logic 0 input voltage -0.3 v 0.8 v v ihclk logic 1 voltage for clock pin (clockin) 3.0 v v cc + 0.3 v v oclk logic 0 voltage for clock pin (clockin) -0.3 v 0.7 v v ihreset logic 1 voltage for reset pin (reset) 2.2 v v cc + 0.3 v output voltages v oh logic 1 output voltage 2.4 v @cp i o = -23 ma v ol logic 0 output voltage 0.33 v @cp i o = 6 ma other i out tri-state output leakage current -5 a 5 a @cp 0 < v out < v cc i in input current -10 a 10 a @cp 0 < v i < v cc c io input/output capacitance 15 pf @cp typical analog input z ai analog input source impedance 9k ? e dnl differential nonlinearity error. difference between the step width and the ideal value. -1 1.5 lsb e inl integral nonlinearity error. maximum deviation from the best straight line through the adc transfer characteristics, excluding the quantization error. +/-1.5 lsb 3.2 ac characteristics see timing diagrams, section 4, for tn numbers. the symbol ? ~ ? indicates active low signal. timing interval tn minimum maximum clock frequency (f clk ) > 0 mhz 20 mhz (note 1) clock pulse width t1 25 nsec clock period (note 2) t2 50 nsec encoder pulse width t3 150 nsec dwell time per state t4 75 nsec ~hostslct hold time t6 0 nsec
MC3310 technical specifications 17 timing interval tn minimum maximum ~hostslct setup time t7 0 nsec hostcmd setup time t8 0 nsec hostcmd hold time t9 0 nsec read data access time t10 25 nsec read data hold time t11 10 nsec ~hostread high to hi-z time t12 20 nsec hostrdy delay time t13 100 nsec 150 nsec ~hostwrite pulse width t14 70 nsec write data delay time t15 35 nsec write data hold time t16 0 nsec read recovery time (note 2) t17 60 nsec write recovery time (note 2) t18 60 nsec read pulse width t19 70 nsec address setup delay time t20 7 nsec data access time t21 19 nsec data hold time t22 2 nsec address setup delay time t23 7 nsec address setup to writeenable high t24 72 nsec ramslct low to writeenable high t25 79 nsec address hold time t26 17 nsec writeenable pulse width t27 39 nsec data setup time t28 3 nsec data setup before write high time t29 42 nsec address setup delay time t30 7 nsec data access time t31 71 nsec data hold time t32 2 nsec address setup delay time t33 7 nsec address setup to writeenable high t34 122 nsec periphslct low to writeenable high t35 129 nsec address hold time t36 17 nsec writeenable pulse width t37 89 nsec data setup time t38 3 nsec data setup before write high time t39 92 nsec read to write delay time t40 50 nsec reset low pulse width t50 5.0 sec ramslct low to strobe low t51 1 nsec strobe high to ramslct high t52 4 nsec writeenable low to strobe low t53 1 nsec strobe high to writeenable high t54 3 nsec periphslct low to strobe low t55 1 nsec strobe high to periphslct high t56 4 nsec note 1 performance figures and timing information valid at f clk = 20.0 mhz only. for timing information and performance parameters at f clk < 20.0 mhz see section 7.1. note 2 the clock low/high split has an allowable range of 45-55%.
MC3310 technical specifications 18 4 i/o timing diagrams for the values of tn , please refer to the table in section 3.2. the host interface timing shown in diagrams 4.4 and 4.5 is only valid when an external logic device is used to provide a parallel communication interfa ce. refer to section 6 for more information. 4.1 clock 4.2 quadrature encoder input 4.3 reset t1 t2 clockin t1 v cc clockin ~reset t50 t3 t3 t4 t4 quad a quad b ~index
MC3310 technical specifications 19 4.4 host interface, 8/16 mode (requires external logic device) 4.4.1 instruction write, 8/16 mode hostdata0-7 ~hostslct hostcmd hostrdy ~hostwrite note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. t7 t6 see note t8 t18 t9 t14 t14 see note t16 t16 t15 t13 t15 low byte high byte 4.4.2 data write, 8/16 mode hostdata0-7 ~hostslct hostcmd hostrdy ~hostwrite note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. t7 t8 t6 t9 t15 see note see note low byte t16 t13 t16 t15 high byte t18 t14 t14
MC3310 technical specifications 20 4.4.3 data read, 8/16 mode hostdata0-7 ~hostslct t7 t8 t19 t6 t9 t13 t11 hostcmd hostrdy ~hostread t12 t10 high-z high-z high-z high byte low byte note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. see note see note 4.4.4 status read, 8/16 mode ~hostslct t7 t8 t17 t6 t9 t11 hostcmd hostdata0-7 ~hostread t12 t10 high-z high-z high-z high byte low byte t19
MC3310 technical specifications 21 4.5 host interface, 16/16 mode (requires external logic device) 4.5.1 instruction write, 16/16 mode t7 t6 t9 t14 t16 t8 t13 t15 ~hostslct hostcmd ~hostwrite hostdata0-15 hostrdy 4.5.2 data write, 16/16 mode t7 t6 t9 t14 t16 t8 t13 t15 ~hostslct hostcmd ~hostwrite hostdata0-15 hostrdy
MC3310 technical specifications 22 4.5.3 data read, 16/16 mode ~hostslct t7 t8 t13 t11 hostcmd hostdata0-15 hostrdy ~hostread t12 t10 high-z high-z t6 t9 t19 4.5.4 status read, 16/16 mode ~hostslct t7 t8 t11 hostcmd hostdata0-15 ~hostread t12 t10 high-z high-z t6 t9 t19
MC3310 technical specifications 23 4.6 external memory timing 4.6.1 external memory read note: pmd recommends using memory with an access time no greater than 15 nsec. 4.6.2 external memory write addr0-addr15 r/~w w/~r ~writeenbl data0-data15 ~ramslct t26 t27 t27 t23 t28 t24 t25 t29 ~strobe t53 t54 ~ramslct addr0-addr15 w/~r ~writeenbl data0-data15 t21 t20 t40 ~strobe t52 t51
MC3310 technical specifications 24 4.7 peripheral device timing 4.7.1 peripheral device read 4.7.2 peripheral device write addr0-addr15 r/~w w/~r ~writeenbl data0-data15 ~periphslct t36 t37 t37 t33 t38 t34 t35 t39 ~strobe t53 t54 ~periphslct addr0-addr15 w/~r ~writeenbl data0-data15 t31 t32 t30 t31 t40 ~strobe t56 t55
MC3310 technical specifications 25 5 pinouts and pin descriptions 5.1 pinouts for MC3310 cp ~writeenbl ~periphslct gnd 3, 8, 14, 20, 29, 37, 46, 56, 59, 61, 71, 92, 104, 113, 120 unassigned 5, 30-34, 38, 39, 42, 45, 48, 49, 51, 55, 57, 95, 105, 106, 107- 109, 131 vcc 2, 7, 13, 21, 35, 36, 40, 47, 50, 52, 60, 62, 66, 93, 103, 121 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 43 44 99 98 58 srlrcv srlxmt srlenable ~hostintrpt clockin data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 4 6 130 129 41 r/~w ~strobe ~ramslct ~reset w/~r 132 1 63 64 poslim1 neglim1 85 86 87 94 72 74 89 75 88 76 83 77 82 axisout1 axisin1 analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 analogvcc analogrefhigh analogreflow analoggnd 84 67 68 quada1 quadb1 69 70 100 101 ~index1 ~home1 pwmmag1 pwmmag2 110 addr0 73 hall1a 90 91 hall1b hall1c 102 pwmmag3 96 pwmsign1 97 pwmsign2 54 nc/synch i/ointrpt 53 prlenable 65 agnd 78-81
MC3310 technical specifications 26 5.2 cp chip pin description table pin name and number direction description ~writeenbl 1 output when low , this signal enables data to be written to the bus. r/~w 4 output this signal is high when the cp chip is performing a read, and low when it is performing a write. ~strobe 6 output this signal is low when the data and address are valid during cp communications. ~periphslct 130 output this signal is low when peripheral devices on the data bus are being addressed. ~ramslct 129 output this signal is low when external memory is being accessed. ~reset 41 input this is the master reset signal. when brought low , this pin resets the processor to its initial conditions. w/~r 132 output this signal is the inverse of r/~w ; it is high when r/~w is low, and vice versa. for some decode circuits, this is more convenient than r/~w . srlrcv 43 input this pin receives serial data from the asynchronous serial port. if serial communication is not used, this pin should be tied to v cc . srlxmt 44 output this pin transmits serial da ta to the asynchronous serial port. srlenable 99 output this pin sets the serial port enable line. sr lenable is always high for the point-to- point protocol and is high during transmission for the multi-drop protocol. ~hostintrpt 98 output when low , this signal causes an interrupt to be sent to the host processor. i/ointrpt 53 input this signal interrupts the cp chip wh en a host i/o transfer is complete. it should be connected to cpintrpt of the parallel interface chip. if the parallel interface is di sabled (see below) this sign al can be left unconnected or tied to v cc . prlenable 65 input this signal enables/disables the para llel communication with the host. if this signal is tied high , the parallel interface is enable d. if this signal is tied low the parallel interface is disabled. see secti on 6 of this manual for more information on parallel communication. warning! this signal should only be tied high if an external logic device that implements the parallel communication logic included in the design. this signal is an output during device reset and as such any connection to gnd or v cc must be via a series resistor. data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 bi-directional multi-purpose data lines. these pins comprise the cp chip?s external data bus, used for all communications with peripheral devices such as external memory or dacs. they may also be used for paralle l-word input and for user-defined i/o operations.
MC3310 technical specifications 27 pin name and number direction description addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 output multi-purpose address lines. these pins comprise the cp chip?s external address bus, used to select devices for communication over the data bus. they may be used for dac output, para llel word input, or user-defined i/o operations. see the pilot motion processor user?s guide for a complete memory map. clockin 58 input this is the clock signal for the motion processor. it is driven at a nominal 20mhz. analogvcc 84 input cp chip analog power supply voltage. this pin must be connected to the analog input supply voltage, which must be in the range 4.5-5.5 v if the analog input circuitry is not used, this pin must be connected to v cc . analogrefhigh 85 input cp chip analog high voltage refere nce for a/d input. the allowed range is analogreflow to analogvcc . if the analog input circuitry is not used, this pin must be connected to v cc . analogreflow 86 input cp chip analog low voltage refere nce for a/d input. the allowed range is analoggnd to analogrefhigh . if the analog input circuitry is not used, this pin must be connected to gnd. analoggnd 87 cp chip analog input ground. this pin must be connected to the analog input power supply return. if the analog input circuitry is not used, this pin must be connected to gnd. analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 74 89 75 88 76 83 77 82 input these signals provide general-purpose analog voltage levels, which are sampled by an internal a/d converter. the a/d resolution is 10 bits. the allowed range is analogreflow to analogrefhigh . any unused pins should be tied to analoggnd. if the analog input circuitry is not used , these pins should be tied to gnd. pwmmag1 pwmmag2 pwmmag3 pwmsign1 pwmsign2 100 101 102 96 97 output these pin provide the pulse width modulated signals for each phase to the motor. the pwm resolution is 9 bi ts at a frequency of 20.0 khz. in 2 or 3-phase pwm 50/50 mode, pw mmag1/2/3 are the only signals and encode both the magnitude and di rection in the one signal. in single-phase pwm sign/magnitude mode, pwmmag1 and pwmsign1 are the pwm magnitude and direction signals respectively. in 2-phase pwm sign/magnitude mo de, pwmmag1 and pwmsign1 are the pwm magnitude and direction signals for phase a. pwmmag2 and pwmsign2, are the pwm magnitude and direction signals for phase b. unused pins may be left unconnected.
MC3310 technical specifications 28 pin name and number direction description quada1 quadb1 67 68 input these pins provide the a and b quadra ture signals for the incremental encoder. when the axis is moving in the positive (f orward) direction, signal a leads signal b by 90. the theoretical maximum encoder pulse ra te is 5.1 mhz. actual maximum rate will vary, depending on signal noise. note : many encoders require a pull-up resistor on each signal to establish a proper high signal. check your encoder?s electrical specification. ~index1 69 input this pin provides the index signal for the incremental encoder. a valid index pulse is recognized by the chip when this signal transitions from high to low . there is no internal gating of the index signal with the encoder a and b inputs. this must be perfor med externally if desired. refer to the application notes section at the end of this manual for an example. ~home1 70 input this pin provides the home signal , general-purpose inputs to the position- capture mechanism. a valid home signal is recognized by the chip when ~home goes low . warning! if this pin is not used, its signal should be tied high. poslim1 63 input this signal provides input from the positive-side (forward) travel limit switch. on power-up or reset this signal defaults to active low interpretation, but the interpretation can be set explicitly using the setsignalsense instruction. warning! if this pin is not used, its signal should be tied high. neglim1 64 input this signal provides input from the ne gative-side (reverse) tr avel limit switch. on power-up or reset this signal defaults to active low interpretation, but the interpretation can be set explicitly using the setsignalsense instruction. warning! if this pin is not used, its signal should be tied high. this signal is an output during device reset and as such any connection to gnd or v cc must be via a series resistor. axisout1 94 output this pin can be programm ed to track the state of any bit in the status registers. if this pin is not used it may be left unconnected. axisin1 72 input this is a general-purpose or programmabl e input. it can be used as a breakpoint input, to stop a motion axis, or to cause an update to occur. if this pin is not used it may be left unconnected. hall1a hall1b hall1c 73 90 91 input hall sensor inputs. each set (a, b, an d c) of signals encodes 6 valid states as follows: a on, a and b on, b on, b and c on, c on, c and a on. a sensor is defined as being on when its signal is high . these signals should only be connected to hall sensors that are mounted at a 120 offset. scheme s that provide hall signals 60 apart will not work. if these pins are not used th ey may be left unconnected. nc/synch 54 input/output on the MC3310 this pin is not used. on the mc3313 this pin is the synchronization signal. in the disabled mode, the pin is configured as an input and is not used. in the master mode, the pin outputs a synchronization pulse that can be used by slave nodes or other devices to synchronize with the internal chip cyc le of the master node. in the slave mode, the pin is configured as an inpu t and a pulse on the pin synchronizes the internal chip cycle.
MC3310 technical specifications 29 pin name and number direction description v cc 2, 7, 13, 21, 35, 36, 40, 47, 50, 52, 60, 62, 66, 93, 103, 121 cp digital supply voltage. all of these pins must be connected to the supply voltage. v cc must be in the range 4.75 - 5.25 v warning! pin 35 must be tied high with a pull-up resistor. a nominal value of 22k ohms is suggested. gnd 3, 8, 14, 20, 29, 37, 46, 56, 59, 61, 71, 92, 104, 113, 120 cp ground. all of these pins must be connected to the power supply return. agnd 78-81 these signals must be tied to analoggnd. if the analog input circuitry is not us ed, these pins must be tied to gnd. unassigned 45, 48, 49, 51, 55, 105, 106, 107, 108, 109 these signals may be connected to gnd for better noise im munity and reduced power consumption or they can be left unconnected (floating). unassigned 5, 30-34, 38, 39, 42, 57, 95, 131 these signals must be left unconnected (floating).
MC3310 technical specifications 30 6 parallel communication with the addition of an external logic device, the pilot motion processor can communicate with a host processor using a parallel data stream. this offers a higher communication rate than a serial interface and may be used in configurations wh ere a serial connection is not available or not convenient. this section details the required logic that must be implemente d in the external device as well as the necessary connections to the cp chip. the reference design files for the parallel interface chip, in actel/viewlogic format, are available from pmd. there are two versions of the design, on e for interfacing with host processors that have an 8-bit data bus and one for host processors that have a 16-bit data bus. the designs are called iopil8 and iopil16 respectively. the interface to the cp chip is essentially identical in both. the function of the i/o chip is to provide a shar ed-memory style interface between the host and cp chip, comprised of four 16-bit wide locations. these are used for transferring commands and data between the host and pilot motion processor. the cp chip accesses the command/data registers using its 16-bit external data bus while the host accesses the registers via a parallel interface with chip select, read, write and comm and/data signals. if necessary, the ho st side interface can be modified by the designer to match specific requirements of the host processor. 6.1 host interface pin description table pin name direction description hostcmd input this signal is asserted high to write a host instruction to the motion processor, or to read the status of the hostrdy and hostintrpt signals. it is asserted low to read or write a data word. hostrdy output this signal is used to synchronize communication between the motion processor and the host. hostrdy will go low (indicating host port busy) at the end of a read or write operation according to the inte rface mode in use, as follows: interface mode hostrdy goes low 8/16 after the second byte of the instruction word after the second byte of each data word is transferred 16/16 after the 16-bit instruction word after each 16-bit data word serial n/a hostrdy will go high, indicating that the host port is ready to transmit, when the last transmission has been processed. all hos t port communications must be made with hostrdy high (ready). a typical busy-to-ready cycle is 12.5 micros econds, but can be substantially longer, up to 100 microseconds. ~hostread input when ~hostread is low , a data word is read fr om the motion processor. ~hostwrite input when ~hostwrite is low , a data word is written to the motion processor. ~hostslct input when ~hostslct is low , the host port is selected for reading or writing operations. cpintrpt output i/o chip to cp chip interrupt. this signal sends an interrupt to the cp chip whenever a host?chipset transmission occurs. it should be connected to cp chip pin 53, i/ointrpt . cpr/~w input this signal is high when the i/o chip is reading data from the i/o chip, and low when it is writing data. it should be connected to cp chip pin 4, r/w . cpstrobe input this signal goes low when the data and address become valid during motion processor communication with peripheral devi ces on the data bus, such as external memory or a dac. it should be connected to cp chip pin 6, strobe .
MC3310 technical specifications 31 pin name direction description cpperiphslct input this signal goes low when a peripheral device on the da ta bus is being addressed. it should be connected to cp chip pin 130, periphslct. cpaddr0 cpaddr1 cpaddr15 input these signals are high when the cp chip is communicating with the i/o chip (as distinguished from any other device on the data bus). they should be connected to cp chip pins 110 ( addr0 ), 111 ( addr1 ), and 128 ( addr15 ). masterclkin input this is the master clock signal for the motion processor. it is driven at a nominal 40 mhz cpclk output this signal provides the clock pulse for the cp chip. its frequency is half that of masterclkin (pin 89), or 20 mhz nominal. it is c onnected directly to the cp chip i/oclk signal (pin 58). hostdata0 hostdata1 hostdata2 hostdata3 hostdata4 hostdata5 hostdata6 hostdata7 hostdata8 hostdata9 hostdata10 hostdata11 hostdata12 hostdata13 hostdata14 hostdata15 bi-directional, tri-state these signals transmit data between th e host and the motion processor through the parallel port. transmission is mediated by the control signals ~hostslct, ~hostwrite, ~hostread and hostcmd . in 16-bit mode, all 16 bits are used ( hostdata0-15 ). in 8-bit mode, only the low- order 8 bits of data are used ( hostdata0-7 ). cpdata0 cpdata1 cpdata2 cpdata3 cpdata4 cpdata5 cpdata6 cpdata7 cpdata8 cpdata9 cpdata10 cpdata11 cpdata12 cpdata13 cpdata14 cpdata15 bi-directional these signals transmit data between the i/o chip and pins data0-15 of the cp chip, via the motion processor data bus.
MC3310 technical specifications 32 6.2 16-bit host interface (iopil16) this design implements a parallel interface with a host processor utilizing a 16-bit data bus. an understanding of the underlying operation of the de sign is only necessary if the designer intends to make modifications. in most ca ses this design can be implemente d without changes. the following notes should be read while referencing the schematics. iopil16 1 is the top level schematic. the timing for the host to i/o chip communication can be found in section 4.5 and the timing for the cp to i/o chip communication can be found in section 4.7. the description below identifies the key elements of each schematic starting with the host side signals. the paragraph title identifies the key schematic(s) being described in the text. iopil16 3 the host interface is shown in sh eet iopil16 3. the incoming da ta hd[15:0] is latched in the transparent latches when ~hg1 and ~hg2 go high. this would be the result of a write from the host to the cp. the latched data hi[15:8] and hi[7:0] go to schematic iopil16 1 and iopil16 5. data from the interface to the host, ho[15:8] and ho[7:0] is enabled onto the host bus, hd[15:0], by hoes2 and hoes1 respectively. the output latches, which present the data during a host read, are always transparent because gout is connected to vdd. the latched i/o is an i/o option on the actel part used and could be omitted in the host interface if a different cpld or fpga does not have this feature. iopil16 1 the control for the host interface starts on iopil16 1. hoes1 and hoes2 are the and of ~hsel and ~hrd and enable read data onto the host bus, as previously described. hrdy is a handshaking signal to the host to allow asynchronous communication between the host and the cp. the host must wait until hrdy is true before attempting to communicate with the cp. this signal is copied as a bit in the host status register. the host status register may be read at any time to determine the state of hrdy, or the hrdy output may be used as an interrupt to the host. ~hsel, ~hrd, ~hwr, and ha0 are the buffered inputs of the host control signals. host interface/iopil16 5 data from the host hi[15:8] and hi[7:0] is written into reg1 and reg2 on the schematic host interface by ~en1 and ~en2. these registers ha ve a 2 to 1 multiplexe d input with both the host data and the cp data being written to these registers. this is convenient for diagnostic purposes and is very efficient in the actel a42mx fp ga's, which are multiplexer based but if the configuration of the logic device used demands it, separate registers could be used for the host and cp data. the schematic for this register is s hown as dfme8. only co mmands and checksums are written to registers reg1 and reg2 while data is written and read from the set of data registers, datreg shown on iopil16 5. these 3 data registers buffer data sent to and from the cp, reducing the number of interrupts the cp must handle. the output from reg1 and reg2, ciq[15:8] and ciq[7:0] go to iopil16 5, where th ey are multiplexed with the other data registers. the multiplexed result, iq[15:8] and iq[7:0], is multiplexed with hst[15:8] and hst[7:0] - the output of the host status registers reg3 and reg4. as previously mentioned, hrdy becomes hst15 so it can be read by the host. the rest of the status register is written by the cp to provide information to the host. ha0 acts as an address bit, and usually is an address bit on the bus. when the host is writing, ha0 low indicates data and ha 0 high indicates a command. when the host is reading, hao low indicates data and ha0 high indica tes status. read status is the only transaction
MC3310 technical specifications 33 allowed while hrdy is low. during a host wr ite the and gate (g1:host interface) and two flops latch the incoming data in the interface latches by drivin g ~hg1, and ~hg2 low from the start of the write transaction until the first negative clock transition after the first positive transition following the start of the write cycle. this tail-bi ting circuit removes the requirement for hold time on the data bus. hictla most of the control logic for the host interface is shown on schematic hi ctla. the sequencer at the top generates hcyc one clock interval after the interface has been accessed and the host has finished the transaction. the nature of the transaction, rd/wr, command/data, and read status is preserved in the three flops f13, f8, and f9. a host write or a cp write, dsiw, enable reg1 and reg2 on the host interface schematic discussed previously. a host data write generates ~enhd1 and ~enhd2 for the data registers on the datreg schematic. the logic at the bottom of the page generates the cp interrupt, the hrdy and the hcmdfl. the hcmdfl is used in the cp status to indicate a command. dsiw, the cp writing to reg1 and reg2 on the host interface schematic clears the interrupt and re asserts hrdy. hrdy is de-asserted during all host transactions except read status, and stays de-asserted until the cp has completed the dsiw cycle that clears the interrupt and reasserts hrdy. as mentioned previously data transfers to and from the host use the data registers and do not interrupt the cp. the cp knows the number of data transfers that must take place after decoding the comm and. it places this number, 0-3, in the 2 least significant bits of the host status register, hst[1: 0]. these become dpnt[1:0] on this page of the schematic and enable an interrupt at 0 for a read and 1 or 0 for a write. the cp always leaves theses bit set to 0 unless setting up a multiple word data transfer. if inten is true and lrdst, latched read status, is false, hcyc will ge nerate an interrupt to the cp. th is will also hold hrdy false until after the cp writes to the interface register, dsiw, thereby generating ~clrflgs. iopil16 4 the cp interface is shown in sheet iopil16 4. the incoming data dsd[15:0] is latched in the transparent latches when ~dg1 an d ~dg2 go high. this occurs at the completion of a write from the cp to the i/o chip. the latched data dsi[15: 8] and dsi[7:0] go to schematic iopil16 1 and iopil16 5. dsi[7:0] also goes to iopil16 2. data from the interface to the cp, do[15:8] and do[7:0] is enabled onto the cp bus, dsd[15:0], by doe2 and doe1 respectively. the output latches, which present the data during a cp read, are always transparent because gout is connected to vdd. the latched i/o in the actel part contains both input and output latches. the output latches could be omitted in the cp interface if a different cpld or fpga does not have this feature. the two incoming cp address bits cpa0 and cpa1 are also latched using ~dg3. the 20ck signal is the clock for the cp. this is a 20 mhz clock derived from a 40 mhz clock input. iopil16 2 the cp control starts on iopil16 2. the i/ o control is generated from ~cpstrb, ~cpis, cpsel and r/w. ~dg1, ~dg2, and ~dg3 latch the incoming data and doe1 and doe2 out- enable the data from this chip to the cp. f2 and f4 tail-bite the write to avoid having to specify hold times on the data. flop f1 divides the 40mhz clock down to 20 mhz. a 20 mhz clock could be used for this interface and the cp.
MC3310 technical specifications 34 dspwa the cp write control is contained on schematic dspw a. the cp interface uses page addressing to save i/o pins. f0, f1 and f2 make up the page register. in addition there are the 2 address bits, la0 and la1. a write to address 0 selects the page register with dsi[2:0] going to the page register and selecting the page for the successive transfers. a read from address 0 reads the status register on all pages. pages 4 and 6 are the only ones implemented in this device. l1 latches the r/w level. the write decoding generates dsiw wh ich enables writes to the dfme8 registers reg1 and reg2 shown on the host interface schematic. dsiw also clears the cp interrupt and restores hrdy. dswst writes to the host status register also shown on the host interface schematic. dswdreg implements writing to the data regist ers shown on iopil16 5 and datreg. finally the logic at the bottom of the page generates cpcyc, a 1-clock interval after the cp cycle is over that implements the actual writes to the registers. the use of the data bus latches and the post bus cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices, without requiring clocking at several times the bus speed. dspra the cp read control is contained on schematic dspra. the 2 by 16 bit mux selects cp status if the cp latched address is 0 and iq[15:0] if the address is not 0. the only significant status bits are bits 15 (indicating the cp is interrupting the host), bits 13 and 14 (both 0 indicating a 16 bit host interface) and bit 0 (set to 1 during a host command transfer and 0 during data transfer). host interface both the cp and the host use a special mode to transfer data to avoid unnecessary cp interrupts. this special mode is under the control of the cp and is transparent to the host. when the cp receives a command from the host it initializes th e transfer by setting the number of transfers expected (0,1,2 or 3) in the 2 lsb's of th e host status register, reg3 and reg4 on host interface. this write (dswst) also loads these bits into the 2 bit down counter dcnt2 on iopil16 5. note that a q8 low, which indica tes a host command, asynchronously clears this register enabling interrupts on schematic hictla. if dpnt[1:0] is not 0 and q8 is high, indicating a host data transfer, and sint goes high indicating the end of a host cycle the counter is decremented. mxad2 selects address ra from the cp latched address bits if the page register contains 6, or the counter contents dpnt[1:0] if not . this allows the cp to have direct access to registers 1, 2, and 3, using addresses 1,2,and 3 on page 6. the host on the other hand can only read or write to the data register, ha0 low and the counter will auto decrement from 3 down to 0 allowing the host to access th e registers on datreg where reg1=r1 and r2, reg2=r3 and r4, and reg3=r5 and r6. the writes are enabled by the two decoders dece2x4, while the reads are selected by the two 4x8 muxes, mux1 and mu x2 controlled by the two 2x1 muxes mds1 and mds0. the output data iq[15:0] goes to host interface sche matic below iopil16 1 and to dspra below iopil16 2. the write data is hi[ 15:8], hi[7:0] from the host and dsi[15:8] and dsi[7:0] from the cp.
hrd hsel hoes1 dspintr out5 ha0 hrd hsel in19 in18 in17 dsiw hstsel hstrd hstwr hwr dspint ho[7:0] dspintr in20 hadr0 st15 dswst hg1 hi[15:8] ho[15:8] hg2 rdy hrdy hi[7:0] hoes2 ciq[7:0] ciq[15:8] q8 sint enhd1 enhd2 iq[15:8] iq[7:0] dsi[7:0] dpnt[1:0] dsi[15:8] st0 hsel hrd hintf clk y b a and2b d pad outbuf pad y inbuf pad y inbuf pad y inbuf drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 pad y inbuf d pad outbuf y b a and2b ciq[15:8] ciq[7:0] clk dsiw dsi[15:8] dsi[7:0] dswst ha0 hcmdfl hi[15:8] hi[7:0] ho[15:8] ho[7:0] hst14 hst15 hst[1:0] iq[15:8] iq[7:0] q8 sint dspintr enhd1 enhd2 hg1 hg2 hrd hsel hwr (hintrfa) host interface iopil16 1 22 oct 2002 dbs
pp4 pp6 g4 g5 cq3 cpis dsiw dswst dsi[7:0] clk r/w cpstrb do[15:0] csel0 cpcyc cpr-w cs doe1 doe2 f1 ib1 clkin 20ck is 20ck csacc cq3 f2 la0 cpsel la1 in27 in28 in26 in30 csacc g1 g2 g3 ckbuf dg3 g6 cq1 f4 40ck csel1 la0 la1 cpsel r/w clk iq[15:0] st0 st15 dspwa dspra strb cpis cpstrb dswdreg qn clk d df1a pad y inbuf d clk q df1 pad y inbuf pad y inbuf pad y inbuf pad y inbuf a b c y nand3b y a clkint d clk q df1 clk cpcyc cpsel dsiw dsi[7:0] dswst la0 la1 pnt0 r/w cpis cpstrb dg3 dswdreg pnt1 pp6 pp4 dspwa do[15:0] iq[15:0] st0 st15 la0 la1 dspra drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 iopil16 2 24 oct 2002 dbs a b c d y and4b a b c d y and4b a b c y nand3b a b c y nand3b csacc a b c d y nand4b dg1 dg2 dg3
vdd vdd hd0 hd1 hd2 hd3 hd4 hd5 hd7 hd8 hd9 hd10 hd11 hd13 hd14 hd15 hg1 hi8 hi9 hi10 hi11 hi12 hi13 hi14 hi15 hi[15:0] hg2 hg1 ho0 ho1 ho2 ho3 ho5 ho6 ho7 ho4 ho[7:0] vdd hoes1 hoes2 hg2 vdd ho8 ho9 ho10 ho11 ho12 ho14 ho15 ho[15:8] ho13 vdd hi1 hi2 hi3 hi4 hi5 hi6 hi7 hi[7:0] hi0 hd6 hd12 y vcc e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 iopil16 3 21 oct 2002 dbs
la1 dsd0 dsd1 dsd12 dsd13 dsd14 dg2 dg2 dsi3 dsi4 dsi5 dsi6 dsi7 dsi2 dsi1 dsi[7:0] do9 do10 do11 do15 do14 do13 do12 do[15:8] do8 doe2 doe2 doe2 doe2 doe1 doe1 doe1 doe1 doe1 cpa0 cpa1 la0 do3 do7 do6 do5 do4 do[7:0] do1 do2 do0 dsi8 dsi9 dsi10 dsi15 dsi14 dsi13 dsi[15:8] dg1 vdd vdd vdd vdd vdd gnd gnd dg3 dg3 clkout 20ck doe2 doe2 doe2 e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g d pad outbuf y vcc dbs iopil16 4 21 oct 2002 doe1 doe1 dsi0 dsd2 dsd3 doe1 doe1 dsd7 dsd6 dsd5 dsd4 doe2 doe2 dsd8 dsd9 dsd10 dsd11 dsi11 doe2 dsi12 dsd15
iq[7:0] iq[15:8] dswst dpinc q8 clk dsi[1:0] pp6 dpnt[1:0] la[1:0] la0 la1 ra[1:0] dpinc dpnt0 dpnt1 q8 sint enhd1 enhd2 dswdreg end1 end2 doe1 dreg a b y or2a a b y or2a drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 data[1:0] sload enable aclr clock q[1:0] dcnt2 data1_[1:0] data0_[1:0] result[1:0] sel0 mxad2 a b c y and3 a b y nand2b dbs iopil16 5 22 oct 2002 pp4 ciq[7:0] ciq[15:8] hi[7:0] hi[15:8] dsi[7:0] dsi[15:8] ra[1:0] la[1:0] pp6 end1 end2 clk ciq[15:8] ciq[7:0] clk dsi[15:8] dsi[7:0] hih[15:8] hi[7:0] iq[15:8] iq[7:0] la[1:0] pp4 pp6 doe1 ra[1:0] end1 end2 datreg
mux1 reg3 reg4 dsiw ha0 hrd hwr ha0 hg2 clk dswst dsla dsl dswst clk dsi[14:8] reg1 ciq[7:0] ciq[15:8] buf1 dsiw hi[7:0] dsi[7:0] buf2 clk hwr hsel g1 dsi[7:2] hg1 ho[15:8] hsel clk hst15 hst[14:8] hst[15:8] hst14 enhd1 enhd2 sint q8 hst[1:0] hst[7:0] hst[7:2] hst[1:0] mux2 ha0 ho[7:0] clk g2 g3 reg2 hi[15:8] dsi[15:8] en1 en2 vdd en1 dspintr hcmdfl hictla en2 iq[15:8] iq[7:0] data1_[7:0] data0_[7:0] result[7:0] sel0 mux2x8 q[5:0] data[5:0] clock enable reg6 q[6:0] data[6:0] clock aclr enable reg7 drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 y a buf y a buf y b a and2b data1_[7:0] data0_[7:0] result[7:0] sel0 mux2x8 d clk qn df1c d clk q df1 a b y nand2 a b y nand2 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 ck dsiw ha0 hcmdfl hrdy q8 sint dspintr en1 en2 enhd1 enhd2 hrd dpnt[1:0] hsel hwr hictla host interface dbs (hintrfa) 24 oct 2002
enhd1 en1 en2 ck vdd ck hcyc hsel dspintr lrdst q9 ck hcyc ha0 hrd hsel hrd hwr hrd hsel clrflgs hwr hsel hwr f1 f2 f3 gnd hcyc g2 g1 hsel hwr ha0 hcyc ck vdd f8 inv3 q8 hcmd f9 inv4 shcmd slrdst g7 f7 inv1 hcyc q2 q1 q1 hrdy f10 g21 f6 f5 hcmdfl ck hwr q8 ck lrdst sintr q8 wren rden dpnt[1:0] dpnt1 dpnt0 inv2 hwr shwr f13 lwr ebsy q1 q2 hcyc q9 hcyc hcmd g19 hccyc dsiw dspintr enhd2 hcyc dsiw g10 vdd hrd hwr lwr clrflgs sint inten ay inv y b a and2a a b y nand2 a b c y nand3b y b a nor2 y b a nor2 a b c d y oa4 d clk q df1 d clk q df1 y vcc d0 d1 d2 d3 s0 s1 clk clr q dfm6a y b a and2b a b c y oa1c cs j clk k clr q jkf2c ay inv cs j clk k clr q jkf2c ay inv a b c y and3b j clk k q jkf ay inv d clk q df1 b 2 a 2 cc d y c nor4 j clk k q jkf d clk q df1 a b c y and3 ay inv y b a and2b cs j clk k clr q jkf2c y b a and2 a b c y or3c a b y nand2b a b y nand2 drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a b c y and3b dbs 21 oct 2002 hictla
cpcyc1 lr/w adw0 cps cps pp4 cpcyc1 pp4 cpcyc1 cpis cpstrb cpsel lr/w la0 la1 dswpnt adw2 adw3 dsiw dswst dsi[7:0] g11 buf2 buf3 cpcyc cpcyc1 gnd q3 g6 q2 clk q2 q3 f4 f5 adw0 dsi0 dsi1 clk dsi2 dswpnt r/w lr/w dg3 l1 dswdreg g12 pp6 pp6 pp4 q3 cpcyc adw2 adw3 dec2 g2 f1 f2 f0 pnt0 pnt2 pnt1 a b c d y and4b y vcc drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a b c y and3 y a buf y a buf a b c y and3b ay inv ay inv y vcc d e clk clr q dfe3a d0 d1 d2 d3 s0 s1 clk clr q dfm6a q g d dl1b a b c y and3 a b c y and3a a b c y and3b a b y2 y3 e y1 y0 dece2x4d a b y nand2 d e clk q dfe1b d e clk q dfe1b d e clk q dfe1b dbs 24 oct 2002 dspwa
$array=12 do[15:0] iq[15:0] st0 st15 ch0 ch15 gnd[12:1] la0 la1 iqsel ch15,gnd,gnd,gnd[12:1],ch0 y gnd y a buf y a buf y a buf drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 data1_[15:0] data0_[15:0] result[15:0] sel0 mux2x16 b y a or2 dspra dbs 24 oct 2002
q4 q7 q6 q5 q3 q2 q1 q0 q[7:0] f7 f6 f5 f4 f3 f2 f1 f0 b4 b0 b1 b2 b3 b5 b6 b7 b[7:0] a4 a0 a1 a2 a3 a5 a7 a[7:0] a6 s ck en1 drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a dfme8 dbs 19 nov. 2002
gnd ra1 dspsel1 hi[7:0] dsi[7:0] hih[15:8] dsi[15:8] en1r3 en2r3 dspsel2 dspsel1 r2[7:0] en2r2 en1r2 dsi[15:8] clk hih[15:8] dsi[7:0] hi[7:0] hi[7:0] dsi[7:0] hih[15:8] dsi[15:8] en1r1 en2r1 r1[15:8] dspsel r2[15:8] r1[7:0] mds1 mds0 mds1 mds0 en2r1 en2r2 en2r3 en1r1 en1r2 en1r3 dspsel pp6 r2 r3 r4 r5 mux1 b1 b2 b3 r3[7:0] r3[15:8] r6 la0 la1 pp4 doe1 iq[15:8] iq[7:0] la[1:0] dspsel2 ra[1:0] ra0 ra1 end1 end2 dec1 dec2 mds0 ra0 gnd mds1 dsir r1 clk clk ciq[7:0] r1[7:0] r3[7:0] r2[7:0] ciq[15:8] r1[15:8] r3[15:8] mux2 r2[15:8] y gnd drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 data3_[7:0] data2_[7:0] data1_[7:0] data0_[7:0] result[7:0] sel1 sel0 mux4x8 y a buf y a buf y a buf a[7:0] b[7:0] ck q[7:0] s en1 dfme8 data0 enable data1 eq3 eq2 eq1 eq0 dece2x4 data0 enable data1 eq3 eq2 eq1 eq0 dece2x4 y d c b a and4a a b y s mx2 a b y s mx2 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 data3_[7:0] data2_[7:0] data1_[7:0] data0_[7:0] result[7:0] sel1 sel0 mux4x8 dbs 24 oct 2002 datreg
MC3310 technical specifications 46 6.3 8-bit host interface (iopil8) this design implements a parallel interface with a host processor utilizing an 8-bit data bus. an understanding of the underlying operation of the de sign is only necessary if the designer intends to make modifications. in most ca ses this design can be implemente d without changes. the following notes should be read while referencing the schematics. iopil16 1 is the top level schematic. the timing for the host to i/o chip communication can be found in section 4.4 and the timing for the cp to i/o chip communication can be found in section 4.7. the description below identifies the key elements of each schematic starting with the host side signals. the paragraph title identifies the key schematic(s) being described in the text. iopil8 3 the host interface for iopil8 is shown in sheet io pil8 3. the incoming data hd[7:0] is latched in the transparent latches when ~hg1 goes high. this would be a write from the host to the cp. the latched data hi[7:0] goes to iopil8 1 and iopil8 5. data from the interface to the host, ho[7:0] is enabled onto the host bus, hd[7:0], by hoes1. the output latches, which present the data during a host read, are always transparent because gout is connected to vdd. the latched i/o is an i/o option on the actel part used and could be omitted in the host interface if a different cpld or fpga does not have this feature. hd[15:8] ar e tri-stated outputs because actel grounds unused i/o pins and this would interfere with using existi ng pmd test equipment. these reserved i/o's can be ommitted in a different implementation with an 8 bit bus. iopil8 1 the control for the host interface starts on io pil8 1. hoes1 is the and of ~hsel and ~hrd, and enable read data onto the host bus, as previously described. hrdy is a handshaking signal to the host to allow asynchronous communication between the host and the cp. the host must wait until hrdy is true before attempting to communicate with the cp. this signal is copied as a bit in the host status register. the host status register may be read at any time to determine the state of hrdy, or the hrdy output may be used as an interrupt to the host. ~hsel, ~hrd, ~hwr, and ha0 are the buffered inputs of the host control signals. host interface/iopil8 5 data from the host hi[7:0] is written into r eg1 and reg2 on the schematic host interface by ~en1 and ~en2. all transfers are 16 bits and take two writes or reads on the 8-bit bus. these registers have a 2 to 1 multiplexed input with both the host data and the cp data being written to this register. this is convenient for diagnostic purposes and is very efficient in the actel a42mx fpga's, which are multiplexer based but if the configuration of th e logic device used demand s it, separate registers could be used for the host and cp data. the schematic for this regi ster is shown as dfme8. only commands and checksums are written to registers reg1 and reg2 while data is written and read from the set of data registers, datreg shown on iopil8 5. these 3 data registers buffer data sent to and from the cp, reducing the number of interrupts the cp must handle. the output from reg1 and reg2, ciq[15:8] and ciq[7:0] go to iopil8 5, where they are multiplexed with the other data registers. the multiplexed result, iq[15:8] and iq[7:0], is multiple xed with hst[15:8] and hst[7:0] - the output of the host status registers reg3 an d reg4. this four input mux, mux4x8, also muxes the 16 bit data onto the 8-bit bus. as previously mentioned hrdy becomes hst15 so it can be read by the host. the rest of the status register is written by the cp to provide information to the
MC3310 technical specifications 47 host. ha0 acts as an address bit, and usually is an address bit on the bus. when the host is writing, ha0 low indicates data and ha0 high indicates a command. when the host is reading, hao low indicates data and ha0 high indi cates status. read status is th e only transaction allowed while hrdy is low. during a host write the and gate (g1:host interface) and two flops latch the incoming data in the interface latches by driving ~hg1 low from the start of the write transaction until the first negative clock transition after the first positive transition following the start of the write cycle. this tail-biting circuit removes the requirement for hold time on the data bus. hictla most of the control logic for the host interface is shown on schematic hi ctla. the sequencer at the top generates hcyc one clock interval after the interface has been accessed and the host has finished the transaction. the nature of the transaction, rd/wr, command/data, and read status is preserved in the three flops f13, f8, and f9. sin ce 16 bit transfers must take place over an 8 bit bus two transfers are required. the toggle flop is used to determine whether a cycle is the first or second of the 2 required. the toggle flop may be initialize d to the 0 state, which indicates that this is the first transfer (high byte), by the cp writing a one to host status bit 15. this status bit is read by the host as the hrdy bit and is not writable by the cp. in addition flop f12 and the associated gating determine if the present command transaction is the first or second byte of a command. if the toggle flop gets into the wrong st ate due to a missed or aborted tran sfer the next command will set it back to the correct state. a host write or a cp write, dsiw, enable reg1 and reg2 on the host interface schematic discussed previously. a host data write generates ~enhd1 and ~enhd2 for the data registers on the datareg schematic. for host writes ~en2, ~en1, ~enhd2, and ~enhd1 are also determined by the state of the toggle flop using hien and loen. 1cmd is used in this logic to ensure co rrect behavior when the command is correcting the state of the toggle. the logic at the bottom of the page generates the cp interrupt, the hrdy and the hcmdfl. the hcmdfl is used in the cp status to indicate a command. dsiw, the cp writing to reg1 and reg2 on the host interface schematic clears the interrupt and reasserts hrdy. hrdy is de-asserted during all host transactions except read status, and stays de-asserted until the cp has completed the dsiw cycle that clears the interrupt an d reasserts hrdy. as mentioned previously data transfer s to and from the host use the data registers and do not interrupt the cp. the cp knows the number of data transfers that must take place after decoding the command. it places this number, 0-3, in the 2 least significant bits of the host status register, hst[1:0]. these become dpnt[1:0] on this page of the schematic and enable an interrupt at 0 for a read and 1 or 0 for a write. the cp always leaves these bits at 0 unless setting up a multiple word data transfer. if inten is true and lrdst, latched read status, is false, hcyc will generate an interrupt to the cp. this will also hold hrdy false until after the cp writes to the interface register, dsiw, thereby generating ~clrflgs. iopil8 4 the cp interface is shown in sh eet iopil8 4. the incoming data dsd[15:0] is latched in the transparent latches when ~dg1 an d ~dg2 go high. this occurs at the completion of a write from the cp to the i/o chip. the latched data dsi[15: 8] and dsi[7:0] go to schematic iopil8 1 and iopil16 5. dsi[7:0] also goes to iopil16 2. data from the interface to the cp, do[15:8] and do[7:0] is enabled onto the cp bus, dsd[15:0], by doe2 and doe1 respectively. the output latches, which present the data during a cp read, are always transparent because gout is connected to vdd. the latched i/o in the actel part contains both input and output latches. the output latches could be omitted in the cp interface if a different cpld or fpga does not have this feature. the two incoming cp address bits cpa0 and cpa1 are also latched using ~dg3. the 20ck signal is the clock for the cp. this is a 20 mhz clock derived from a 40 mhz clock input.
MC3310 technical specifications 48 iopil8 2 the cp control starts on iopil8 2. the i/o co ntrol is generated from ~cpstrb, ~cpis, cpsel and r/w. ~dg1, ~dg2, and ~dg3 latch the incoming data and doe1 and doe2 out-enable the data from this chip to the cp. f2 and f4 tail-bite the write to avoid having to specify hold times on the data. flop f1 divides the 40mhz clock down to 20 mhz. a 20 mhz clock could be used for this interface and the cp. dspwa the cp write control is contained on schematic dspw a. the cp interface uses page addressing to save i/o pins. f0, f1 and f2 make up the page register. in addition there are the 2 address bits, la0 and la1. a write to address 0 selects the page register with dsi[2:0] going to the page register and selecting the page for the successive transfers. a read from address 0 reads the status register on all pages. pages 4 and 6 are the only ones implemented in this device. l1 latches the r/w level. the write decoding generates dsiw wh ich enables writes to the dfme8 registers reg1 and reg2 shown on the host interface schematic. dsiw also clears the cp interrupt and restores hrdy. dswst writes to the host status register also shown on the host interface schematic. dswdreg implements writing to the data regist ers shown on iopil8 5 and datreg. finally the logic at the bottom of the page generates cpcyc, a 1-clock interval after the cp cycle is over that implements the actual writes to the registers. the use of the data bus latches and the post bus cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices, without requiring clocking at several times the bus speed. dspra the cp read control is contained on schematic dspra. the 2 by 16 bit mux selects cp status if the cp latched address is 0 and iq[15:0] if the address is not 0. the only significant status bits are bits 15 (indicating the cp is interrupting the host), bit 14 (1 indicating an 8-bit host interface) and bit 0 (set to 1 during a host command transfer and 0 during data transfer). host interface both the cp and the host use a special mode to transfer data to avoid unnecessary cp interrupts. this special mode is under the control of the cp and is transparent to the host. when the cp receives a command from the host it initializes th e transfer by setting the number of transfers expected (0,1,2 or 3) in the 2 lsb's of th e host status register, reg3 and reg4 on host interface. this write (dswst) also loads these bits into the 2 bit down counter dcnt2 on iopil8 5. note that a q8 low, which indicates a host command, asynchronously clears this register enabling interrupts on schematic hi ctla. if dpnt[1:0] is not 0 and q8 is high, indicating a host data transfer, and sint goes high indicating the end of a host cycle the counter is decremented. mxad2 selects address ra from the cp latched address bits if the page register contains 6, or the counter contents dpnt[1:0] if not. this allows the cp to have direct access to registers 1, 2, and 3, using address 1,2,and 3 on page 6. the host on the other hand can only read or write to the data register, ha0 low and the counter will auto decrement from 3 down to 0 allowing the host to access the registers on datareg where reg1=r1 an d r2, reg2=r3 and r4, and reg3=r5 and r6. the writes are enabled by the two decoders dece2 x4 while the reads are selected by the two 4x8 muxes, mux1 and mux2 controlled by the two 2x1 muxes mds1 and mds0. the output data iq[15:0] goes to host inter face schematic below iopil8 1 an d to dspra below iopil8 2. the write data is hi[7:0] from the host and dsi[15: 8] and dsi[7:0] from the cp. note that end1
MC3310 technical specifications 49 and end2, the write enables, are both high for dswdreg, while they are high one at a time for host writes controlled by the toggle flop. sint en ables dpinc only when the toggle is high after the second transfer.
hrd hsel hoes1 dspintr out5 ha0 hrd hsel in19 in18 in17 dsiw hstsel hstrd hstwr hwr clk dspint ho[7:0] in20 hadr0 dswst rdy hrdy hi[7:0] ciq[7:0] ciq[15:8] q8 sint enhd1 enhd2 iq[7:0] dsi[7:0] dpnt[1:0] dsi[15:8] iq[15:8] hintf dspintr st0 hg1 st15 y b a and2b d pad outbuf pad y inbuf pad y inbuf pad y inbuf drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 pad y inbuf d pad outbuf ciq[15:8] ciq[7:0] clk dsiw dsi[15:8] dsi[7:0] dswst ha0 hcmdfl hi[7:0] ho[7:0] hst14 hst15 hst[1:0] iq[15:8] iq[7:0] q8 sint dspintr enhd1 enhd2 hg1 hrd hsel hwr (hintrfa) host interface dbs iopil8 1 22 oct 2002
st0 csacc g4 g5 cq3 cpis strb dsi[7:0] r/w do[15:0] csel0 cpr-w cs f1 ib1 clkin 20ck 20ck csacc cq3 f2 la0 cpsel la1 in27 in28 in26 in30 csacc g1 g3 ckbuf dg3 g6 cq1 f4 40ck csel1 la0 la1 cpis cpsel cpstrb r/w clk cpcyc st15 iq[15:0] dspra g2 is doe1 doe2 dg1 dg2 dg3 dswdreg dsiw dswst pp4 pp6 cpstrb clk dspwa a b c y nand3b a b c y nand3b drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 qn clk d df1a pad y inbuf d clk q df1 pad y inbuf pad y inbuf pad y inbuf pad y inbuf a b c y nand3b a b c d y and4b y a clkint a b c d y nand4b d clk q df1 do[15:0] la0 la1 st0 st15 iq[15:0] dspra a b c d y and4b clk cpcyc cpsel dsi[7:0] dswdreg dswst la0 la1 pnt0 pnt1 r/w cpis cpstrb dg3 dsiw pp4 pp6 dspwa dbs 30 oct 2002 iopil8 2
vdd hd0 hd1 hd2 hd3 hd4 hd5 hd6 hd7 hg1 hi0 hi1 hi2 hi3 hi4 hi5 hi6 hi7 hi[7:0] hg1 ho0 ho1 ho2 ho3 ho5 ho6 ho7 ho4 ho[7:0] vdd hoes1 vdd hd10 hd11 hd12 hd14 hd15 hd8 hd9 hd13 d e pad tribuff d e pad tribuff d e pad tribuff d e pad tribuff d e pad tribuff d e pad tribuff d e pad tribuff d e pad tribuff y gnd y vcc e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g avoid loading 16 bit busses iopil8 3 hi byte tristate to 24 oct 2002 dbs
la1 dsd0 dsd1 dsd2 dsd3 dsd4 dsd5 dsd6 dsd7 dsd8 dsd9 dsd10 dsd11 dsd12 dsd13 dsd14 dsd15 dg2 dg2 do9 do10 do11 do15 do14 do13 do12 do[15:8] do8 doe2 doe2 doe2 doe2 doe2 cpa0 cpa1 la0 do3 do7 do6 do5 do4 do[7:0] do1 do2 do0 dsi8 dsi9 dsi10 dsi11 dsi15 dsi14 dsi13 dsi12 dsi[15:8] dg1 vdd vdd vdd vdd vdd gnd gnd dg3 dg3 clkout 20ck doe2 doe2 doe2 doe2 doe2 dsi4 dsi5 dsi6 dsi7 dsi2 dsi1 dsi0 dsi[7:0] dsi3 doe1 doe1 doe1 doe1 doe1 doe1 doe1 doe1 doe1 e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g e d gout gin pad q high slew q d g q bbdlhs d g d pad outbuf y vcc dbs 22 oct 2002 iopil8 4
pp6 iq[7:0] iq[15:8] dswst dpinc q8 clk dsi[1:0] pp6 dpnt[1:0] la[1:0] la0 la1 ra[1:0] la[1:0] end1 end2 ra[1:0] dpinc dpnt0 dpnt1 q8 sint enhd1 enhd2 dswdreg end1 end2 dreg dsi[15:8] dsi[7:0] hi[7:0] ciq[15:8] ciq[7:0] clk doe1 pp4 a b y or2a a b y or2a drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 data[1:0] sload enable aclr clock q[1:0] dcnt2 data1_[1:0] data0_[1:0] result[1:0] sel0 mxad2 a b c y and3 a b y nand2b ciq[15:8] ciq[7:0] clk dsi[15:8] dsi[7:0] hi[7:0] iq[15:8] iq[7:0] la[1:0] pp4 pp6 doe1 ra[1:0] end1 end2 datreg dbs 22 oct 2002 iopil8 5
reg3 reg4 dsiw ha0 hrd hwr clk dswst dsla en2 dsl dsi[15:8] dswst clk dsi[14:8] reg1 ciq[7:0] buf1 buf2 hwr hsel g1 dsi[7:2] hg1 rstog hsel clk dswst dsi15 rstog enhd1 enhd2 sint q8 hst[1:0] clk reg2 clk g2 iq[7:0] ho[7:0] dsiw dsi[7:0] hi[7:0] en1 hi[7:0] ciq[15:8] vdd hictla en1 toggle en2 dspintr hcmdfl hst[7:0] hst[7:2] hst[1:0] iq[15:8] hst[15:8] hst[14:8] hst14 hst15 hst[15:8] toggle ha0 ay inv d clk qn df1c q[5:0] data[5:0] clock enable reg6 q[6:0] data[6:0] clock aclr enable reg7 a b y nand2 drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 y a buf y a buf y b a and2b a[7:0] b[7:0] ck q[7:0] s en1 dfme8 d clk q df1 a b y nand2 data3_[7:0] data2_[7:0] data1_[7:0] data0_[7:0] result[7:0] sel1 sel0 mux4x8 ck dpnt[1:0] dsiw hcmdfl hrdy q8 sint toggle dspintr en1 en2 enhd1 enhd2 hrd hsel hwr rstog ha0 hictla selects [15:8], hi byte first dbs toggle lo 24 aug 2001 (hintrfa) host interface
ck vdd ck hcyc hsel hcyc dspintr dspintr lrdst q9 vdd ck hcyc ha0 hrd hsel loen hwr hrd hsel clrflgs hwr hsel hwr hwr hien f1 f2 f3 gnd hcyc g2 g12 g14 hsel hwr ha0 hcyc ck vdd inv3 q8 hcmd shcmd g7 f7 hcyc q2 q1 q1 hrdy f10 g21 f6 f5 f4 hcmdfl ck lcmd ck hcyc f12 en1 en2 hien hwr q8 enhd2 enhd1 ck enintr lrdst sintr clrflgs sint inten q8 wren rden dpnt[1:0] dpnt1 dpnt0 inv2 hwr shwr f13 lwr ebsy q1 q2 hcyc q9 hcyc hcmd g19 hccyc ck hcyc rstog toggle 1cmd q8 toggle 1cmd toggle 1cmd toggle 1cmd dsiw 1cmd hwr g1 inv1 hrd hrd dsiw dsiw lwr loen g10 slrdst f8 f9 inv4 ay inv y b a and2a y b a and2a a b y nand2a a b c d y oa4 d clk q df1 d clk q df1 y vcc d0 d1 d2 d3 s0 s1 clk clr q dfm6a y b a and2b a b c y aoi1 a b c y aoi1 ay inv a b c y and3b j clk k q jkf d clk q df1 b 2 a 2 cc d y c nor4 j clk k q jkf d clk q df1 d e clk clr q dfe3a d e clk q dfe b c a y nand3 b c a y nand3 a b c y and3 a b c y nand3b a b y nand2b a b c y or3c ay inv y b a and2b cs j clk k clr q jkf2c y b a and2 y b a and2a a b y or2a a b c y and3a drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a b c y oa1c ay inv a b c y and3b cs j clk k clr q jkf2c cs j clk k clr q jkf2c ay inv toggle lo (1st byte) ld hi, rd hi hictla 22 oct 2002 dbs
q3 adw2 pnt2 pnt1 pnt0 cpcyc1 lr/w adw0 cps cps pp4 cpcyc1 pp4 cpcyc1 cpis cpstrb cpsel lr/w la0 la1 adw2 adw3 dsiw dswst cpcyc dsi[7:0] g12 buf2 buf3 cpcyc cpcyc1 gnd q3 g6 q2 clk q2 q3 f4 f5 adw0 dec2 dsi0 dsi1 clk dsi2 f0 f1 f2 r/w lr/w dg3 l1 g2 pp6 pp4 pp6 adw3 g11 dswpnt dswpnt dswdreg a b c y and3b y vcc drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a b c y and3 y a buf y a buf a b c y and3b ay inv ay inv y vcc d e clk clr q dfe3a d0 d1 d2 d3 s0 s1 clk clr q dfm6a a b y2 y3 e y1 y0 dece2x4d d e clk q dfe1b d e clk q dfe1b d e clk q dfe1b q g d dl1b a b y nand2 a b c y and3a a b c y and3 a b c d y and4b dbs 24 oct 2002 dspwa
iqsel la0 la1 st0 st15 ch0 ch15 iq[15:0] gnd[12:1] do[15:0] vdd gnd $array=12 ch15,vdd,gnd,gnd[12:1],ch0 data1_[15:0] data0_[15:0] result[15:0] sel0 mux2x16 y gnd b y a or2 y a buf drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 y a buf y vcc y a buf dspra dbs 30 oct 2002
q4 q7 q6 q5 q3 q2 q1 q0 q[7:0] f7 f6 f5 f4 f3 f2 f1 f0 b4 b0 b1 b2 b3 b5 b6 b7 b[7:0] a4 a0 a1 a2 a3 a5 a7 a[7:0] a6 ck en1 s drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a a b s e clk q dfme1a dfme8 dbs 19 nov. 2002
gnd end2 end1 ra1 ra0 ra[1:0] dspsel2 dspsel1 hi[7:0] dsi[7:0] hi[7:0] clk dsi[15:8] en1r3 en2r3 dspsel2 dspsel1 r2[7:0] en2r2 en1r2 dsi[15:8] clk hi[7:0] dsi[7:0] hi[7:0] hi[7:0] dsi[7:0] hi[7:0] dsi[15:8] en1r1 r1[15:8] dspsel r2[15:8] r1[7:0] mds1 mds0 mds0 la[1:0] dspsel pp6 r1 r3 r4 r5 mux1 mux2 b1 b2 b3 r3[7:0] r3[15:8] r6 la0 pp4 doe1 iq[15:8] iq[7:0] en1r3 en1r2 en1r1 en2r3 en2r2 en2r1 dsir dsir la1 ra0 gnd ra1 mds0 mds1 r2 en2r1 clk ciq[7:0] r1[7:0] r3[7:0] r2[7:0] mds1 r1[15:8] r3[15:8] ciq[15:8] r2[15:8] a b y s mx2 drawn by: 4 3 2 1 d c b a a b c d 1 2 3 4 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 a[7:0] b[7:0] ck q[7:0] s en1 dfme8 data3_[7:0] data2_[7:0] data1_[7:0] data0_[7:0] result[7:0] sel1 sel0 mux4x8 data3_[7:0] data2_[7:0] data1_[7:0] data0_[7:0] result[7:0] sel1 sel0 mux4x8 y a buf y a buf y a buf a[7:0] b[7:0] ck q[7:0] s en1 dfme8 data0 data1 enable eq0 eq1 eq2 eq3 dece2x4 data0 data1 enable eq0 eq1 eq2 eq3 dece2x4 y d c b a and4a y gnd a b y s mx2 dbs 30 oct 2002 datreg a[7:0] b[7:0] ck q[7:0] s en1 dfme8
MC3310 technical specifications 61
MC3310 technical specifications 62 7 application notes 7.1 design tips the following are recommendations for the design of circuits that utilize a pmd motion processor. serial interface if the serial configuration decode logic is not implemented (see section 7.2) the cp data bus should be tied high. this plac es the serial interface in a default c onfiguration of 9600,n,8,1 after power on or reset. controlling pwm output during reset when the motion processor is in a reset state (when the reset line is held low) or immediately after a power on, the pwm outputs can be in an unknown st ate, causing undesirable motor movement. it is recommended that the enable line of any motor amp lifier be held in a disa bled state by the host processor or some logic circuitry until communication to motion processor is established. this can be in the form of a delay circuit on the amplifier en able line after power up, or the enable line can be anded with the cp reset line. parallel word encoder input when using parallel word input for motor position, it is useful to also decode this information into the user i/o space. this allows the current input value to be read using th e chip instruction readio for diagnostic purposes. using a non standard system clock frequency it is often desirable to share a common clock among several components in a design. in the case of the pmd motion processors it is possible to use a cl ock below the standard value of 20mhz. in this case all system frequencies will be reduced as a fraction of the input clock verses the standard 20mhz clock. the list below shows the affected system parameters:- ? serial baud rate ? pwm carrier frequency ? timing characteristics as shown in section 3.2 ? cycle time ? commutation rate for example, if an input clock of 17mhz is used with a serial baud rate of 9600 th e following timing changes will result:- ? serial baud rate decreases to 9600 bps *17/20 = 8160 bps ? pwm frequency decreases to 20 khz *17/20 = 17 khz
MC3310 technical specifications 63 ? cycle time increases to 153.6 sec *20/17 = 180.71 sec ? commutation rate decreases to 20khz *17/20 = 17 khz
MC3310 technical specifications 64 7.2 rs-232 serial interface the interface between the MC3310 chip and an rs-232 serial port is shown in the following figure. comments on schematic s1 and s2 encode the characteristics of the serial port such as baud rate, number of stop bits, parity, etc. the cp will read these switches during init ialization, but these parameters may also be set or changed using the setserialport chipset command. the db9 connector wired as shown can be connected directly to the serial port of a pc without requiring a null modem cable.
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a female db9 wired as shown will connect to a pc without a dummy modem. u2 and u3 could be imple mented in a pld b rs232 serial interface performance motion devices 55 old bedford rd lincoln, ma 01773 b 10 monday, july 07, 2003 title size document number rev date: sheet of vcc a0 a1 ds0 a2 ds1 a3 ds2 a4 ds3 a5 ds4 a6 ds5 a7 ds6 a8 ds7 a9 ds8 a10 ds9 a11 ds10 a12 ds11 a13 ds12 a14 ds13 a15 ds14 ds15 is- r/w strb- vcc c1+ c1- v+ c2+ v- c2- serxmit txd serrcv rxd gnd rs- clk gnd ds[0..15] a[0..15] ds4 sw8 sw6 vcc sw7 ds1 sw6 ds6 sw1 ds7 sw15 sw13 sw13 sw14 sw8 ds5 ds[0..15] ds10 sw2 ds12 ds8 sw16 sw5 sw16 sw10 sw12 ds14 sw3 sw9 sw15 sw11 ds15 ds9 is- ds0 a9 sw9 sw4 ds[0..15] sw12 sw11 sw1 sw2 ds3 sw14 sw4 r/w ds13 ds2 sw5 ds11 sw7 vcc sw10 sw3 strb- c5 .1uf 50v rs1 rsip9 1 2 3 4 5 6 7 8 9 com r1 r2 r3 r4 r5 r6 r7 r8 c3 .1uf 50v c1 .1uf 50v rs2 rsip9 1 2 3 4 5 6 7 8 9 com r1 r2 r3 r4 r5 r6 r7 r8 s1 sw dip-8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 u3 ad232 1 3 4 5 11 10 12 9 2 6 14 7 13 8 c1+ c1- c2 c2- t1in t2in r1out r2out v+ v- t1out t2out r1in r2in u2 not 1 2 j1 connector db9 5 9 4 8 3 7 2 6 1 u2 not 1 2 c4 .1uf 50v r? 22k u2 74ls244 2 4 6 8 11 13 15 17 1 19 18 16 14 12 9 7 5 3 1a1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 1g 2g 1y1 1y2 1y3 1y4 2y1 2y2 2y3 2y4 c2 .1uf 50v s2 sw dip-8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 u2 nand4 1 2 3 4 5 u3 74ls244 2 4 6 8 11 13 15 17 1 19 18 16 14 12 9 7 5 3 1a1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 1g 2g 1y1 1y2 1y3 1y4 2y1 2y2 2y3 2y4 u1 cp2n11 13 60 14 20 9 10 11 12 15 16 17 18 19 22 23 24 47 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 129 130 4 6 1 25 26 27 28 29 46 59 61 71 92 104 113 120 21 40 62 93 103 121 58 7 2 41 36 50 56 35 132 63 64 94 100 96 72 98 43 44 53 99 74 89 75 88 76 83 77 82 84 85 86 87 3 8 37 131 67 69 70 68 52 101 102 97 73 90 91 65 54 vcc vcc gnd gnd data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 vcc addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 ~ramslct ~periphslct r/~w ~strobe ~writeenbl data12 data13 data14 data15 gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc vcc clockin vcc vcc ~reset vcc vcc gnd ~rs w/~r poslim1 neglim1 axisout1 pwmmag1 pwmsign1 axisin1 ~hostintrpt srlrcv srlxmt i/ointrpt srlenable analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 analogvcc analogrefhigh analogreflow analoggnd gnd gnd gnd n/c quada1 ~index1 ~home1 quadb1 vcc pwmmag2 pwmmag3 pwmsign2 hall1a hall1b hall1c prlenable synch
MC3310 technical specifications 66 7.3 rs 422/485 serial interface the interface between the MC3310 chip and an rs-4 22/485 serial port is shown in the following figure. comments on schematic use the included table to determine the jumper setup that matches the chosen configuration. if using rs485, the last cp must have its jumpers set to rs485 last. the db 9 connector wiring is for example only. the db9 should be wired acco rding to the specificat ion that accompanies the connector to which it is attached. for correct operation, logic should be provided that contains the start up serial configuration for the motion processor. refer to the rs232 serial inte rface schematic for an example of the required logic. note that the rs485 interface cannot be used in point to point mode. it can only be used in a multi- drop configuration where the chip srlenable line is used to control transmit/receive operation of the serial transceiver. chips in a multi-drop environment sh ould not be operated at different ba ud rates. this will result in communication problems.
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a to host rs422 rs485 rs485 last com type jp1 jp2 jp3 jp4 1-2 1-2 2-3 2-3 2-3 2-3 1-2 1-2 1-2 2-3 1-2 1-2 note:rs422 is capable of full duplex and uses 2 pairs. rs485 is half-duplex on 1 pair and may be daisy chained rs422 host as shown in the table. the cp uses rs485. a single cp may communicate with an a single pair may be wired to either p1-1,9 or p1-2,3 for rs485. terminate terminate transmit tx-rx + tx-rx - receive a rs422/485 interface performance motion devices 55 old bedford rd lincoln, ma 01773 b 11 thursday, april 11, 2002 title size document number rev date: sheet of vcc tx+ tx- vcc gnd rx+ rx- gnd rxt txt r3 4.7k jp4 jmp3 1 2 3 jp1 jmp3 1 2 3 r1 120 jp3 jmp3 1 2 3 u1 max491 5 9 10 12 11 2 4 3 14 7 6 di y z a b ro de re vcc gnd gnd + c1 4.7uf 10v tant c2 .1uf 50v cer r2 120 p1 connector db9 rt angle male 5 9 4 8 3 7 2 6 1 jp2 jmp3 1 2 3 srlrcv srlxmt srlenable
MC3310 technical specifications 68 7.4 pwm motor interface the following schematic sh ows a typical interface circuit betw een the MC3310 and an amplifier used in pwm 50/50 output mode. comments on schematic the l6234 from st microelectronics is an integrated package that pr ovides 3 half-bridge amplifiers on a single chip. it can drive up to 2 amps continuous at 52 volts.
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a axis1 diodes and caps should be rated 2-3 times mpwr voltage bootstrap diodes and caps typical note:l6234 available from st microelectronics formerly sgs-thompson axis 1 a 3 phase pwm 50/50 performance motion devices 55 old bedford rd lincoln, ma 01773 b 1 1 tuesday, november 19, 2002 title size document number rev date: sheet of mpw r mgnd vcc pwm1a pwm1b pwm 1c mgnd en quada1 indx1 quadb1 hom e1 pwm1a pwm 1c pwm1b gnd vcc c? 1uf d? 1n414 8 c? .1uf hf cer r? 22 k u? l62 34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 in1 en1 in2 en2 in3 en3 vcp out1 out2 out3 vref sense gnd vs vboot d? 1n414 8 c? .01uf + c? 100uf c? .22uf r? 15 k u1 cp24n11 13 60 14 20 9 10 11 12 15 16 17 18 19 22 23 24 47 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 129 130 4 6 1 25 26 27 28 29 46 59 61 71 92 104 113 120 21 40 62 93 103 121 58 7 2 41 36 50 56 35 132 63 64 94 100 96 72 98 43 44 53 99 74 89 75 88 76 83 77 82 84 85 86 87 3 8 37 131 67 69 70 68 52 101 102 97 73 90 91 65 54 vcc vcc gnd gnd data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 vcc addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 ~ramslct ~periphslct r/~w ~strobe ~writeenbl data12 data13 data14 data15 gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc vcc clockin vcc vcc ~reset vcc vcc gnd ~rs w/~r poslim1 neglim1 axisout1 pwmmag1 pwmsign1 axisin1 ~hostintrpt srlrcv srlxmt i/ointrpt srlenable analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 analogvcc analogrefhigh analogreflow analoggnd gnd gnd gnd n/c quada1 ~index1 ~home1 quadb1 vcc pwmmag2 pwmmag3 pwmsign2 hall1a hall1b hall1c prlenable synch mtr1a mtr1b mtr 1c
MC3310 technical specifications 70 7.5 12-bit parallel dac interface the interface between the MC3310 chip and a quad 12 bit dac is shown in the following figure. comments on schematic the 12 data bits are written to the dac addressed by address bits a0 and a1 in quad dac 1, when a2 is 0. in this fashion cp address 4000h is used for axis 1, phase a, and 4001h is used for axis 1 phase b.
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a it is generally not necessary provided for vrefh and vrefl if clean supplies +- 10v are 0x4000+ 0,1,2,3 . to provide offset adjust. 4 dacs @ cp ad r the logic within the dotted lines is easily implemented within a cpld. a 2 or 3 phase 12-bit dac out performance motion devices 55 old bedford rd lincoln, ma 01773 b 1 1 tuesday, november 19, 2002 title size document number rev date: sheet of vcc ds0 ds1 ds2 ds3 ds4 ds5 ds6 ds7 ds8 ds9 ds10 ds11 ds12 ds13 ds14 ds15 is- strb- we- rs- clk gnd ds[0..15] vrefh ds13 vrefl ds7 a0 dacva2 ds6 gnd ds11 a1 ds12 vss gnd ds9 ds8 vdd ds[4..15] ds5 ds10 gnd rs- dacvb1 dacvb2 ds4 cs1- vcc dacva1 ds15 ds14 a14- a7 a5 a1 2 a[0..15] a4 is- cs1- a1 1 a1 0 a0 a1 3 a2 a2 we - a6 a1 a1 4 a1 5 a9 a3 a8 strb - u1 cp24n1 13 60 14 20 9 10 11 12 15 16 17 18 19 22 23 24 47 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 129 130 4 6 1 25 26 27 28 29 46 59 61 71 92 104 113 120 21 40 62 93 103 121 58 7 2 41 36 50 56 35 132 63 64 94 100 96 72 98 43 44 53 99 74 89 75 88 76 83 77 82 84 85 86 87 3 8 37 131 67 69 70 68 52 101 102 97 73 90 91 65 54 vcc vcc gnd gnd data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 vcc addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 ~ramslct ~periphslct r/~w ~strobe ~writeenbl data12 data13 data14 data15 gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc vcc clockin vcc vcc ~reset vcc vcc gnd ~rs w/~r poslim1 neglim1 axisout1 pwmmag1 pwmsign1 axisin1 ~hostintrpt srlrcv srlxmt i/ointrpt srlenable analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 analogvcc analogrefhigh analogreflow analoggnd gnd gnd gnd n/c quada1 ~index1 ~home1 quadb1 vcc pwmmag2 pwmmag3 pwmsign2 hall1a hall1b hall1c prlenable synch r? 22k u? or5 1 2 3 4 5 6 u7 burr-brown 7724,7725 so or plcc 24 25 1 5 4 28 8 9 10 11 12 13 14 15 16 17 18 19 20 23 22 21 7 3 2 27 26 6 vlog vdd vrefh gnd vss vrefl db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 r/w /cs a0 a1 /ldac vouta voutb voutc voutd /reset
MC3310 technical specifications 72 7.6 16-bit serial dac interface the following schematic shows an interface circuit between the MC3310 and a dual 16-bit serial dac. comments on schematic the 16 data bits from the cp chip are latched in the two 74h165 shift registers when the cp writes to address 400x hex, and the address bits a1 and a2 are latched in the 2 dlat latches and decoded by the 138 cpu cycle. the fed-back and-or gate la tches, the decoded wrf, and the next clock will clear the 1 st sequencer flop dff3. this will disable th e wrf latch and the second clock will clear the second dff3 flop, forcing dacwrn low, and setting the first flop since wrf will have gone high. dacwrn low will clear the 74109, shftcn tn. the 4 bit counter, 74161, is also parallel loaded to 0, and the counter is enabled by enp going high. the counter will not start counting nor the shift register start shifting until the clock after the dacwrn flop sets since the load overrides the count enable. when the dacwr fl op is set the shift register will start shifting and the counter will count the shifts. after 15 shifts cnt15 from th e counter will go high and the next clock will set the daclat flop and set the shftcntn flop. this will stop the shift after 16 shifts and assert l1 through l4 depending on the address stored in the latch. the 16th clock also was counted causing the counter to roll over to 0 and cnt15 to go low. the ne xt clock will therefore clear the daclat flop causing the dac latch signal l1 through l4 to terminate and the 16 bits of data to be latched in the addressed dac. the control logic is now back in its or iginal state waiting for the next write to the dacs by the cp. serck is a 10mhz clock, the 20mhz cp clock divided by 2, since the ad1866 dacs will not run at 20mhz.
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a axis 1 amp shown typical of all 4 axis the module ports represent inputs and outputs from the cpld all logic labelled u2 may be implemented in a cpld all input signals are common to the cp. a serial dac out performance motion devices 55 old bedford rd lincoln, ma 01773 b 1 0 thursday, april 11, 2002 title size document number rev date: sheet of dacl serck gnd gnd clk ds0 ds1 ds2 ds3 ds4 a1 4 a14n ds5 a0 is- ds6 a1 a0 wrf ds7 a2 r/w ldn a1 4 strb - is- clkinh r/w shtcntn strb - clk rs- rs- wrf dacwrn ds8 ds9 ds10 ds11 ds12 rs- ds13 ds14 ds15 serd vcc serck vcc 5v a shftcntn vb 1 a1 l1 sda t l2 l1 vo 1 gnd l3 l4 vcc sda t dacl serck gnd dacl l2 vo 2 a2 vb 2 wrf serck gnd vcc 5v a vb 3 +1 2va l3 vo 3 vo1 dacv1 l4 vo 4 vb 4 -12v a vb1 gnd ds[0..15] ds[0..15] gnd ldn u2 dff 1 2 3 q d clk u2a 741 09 2 4 3 6 7 5 1 j clk k q q pr cl u2 741 61 3 4 5 6 7 10 2 9 1 14 13 12 11 15 a b c d enp ent clk load clr qa qb qc qd rco u2 not 1 2 u2 not 1 2 u2 no t 1 2 r3 10 0k u2 nor2 1 2 3 u2 741 65 10 11 12 13 14 3 4 5 6 2 15 1 9 7 ser a b c d e f g h clk inh sh/ld qh qh u2 and3 1 2 3 4 u2 or2 1 2 3 u2 dla t 1 2 3 q d g u2 138 1 2 3 6 4 5 15 14 13 12 11 10 9 7 a b c g1 g2a g2b y0 y1 y2 y3 y4 y5 y6 y7 u4 ad1866 2 3 5 6 1 15 7 12 9 4 16 14 13 11 10 8 ll dl dr lr vl vs dgnd agnd vs clk vbl vol nrl nrr vor vbr u3 ad1866 2 3 5 6 1 15 7 12 9 4 16 14 13 11 10 8 ll dl dr lr vl vs dgnd agnd vs clk vbl vol nrl nrr vor vbr r1 10 k u2 or2 1 2 3 u2 dla t 1 2 3 q d g u? or5 1 2 3 4 5 6 u2 no t 1 2 + - u4a op4 97 3 2 1 4 13 u2 741 65 10 11 12 13 14 3 4 5 6 2 15 1 9 7 ser a b c d e f g h clk inh sh/ld qh qh u2a 74l s74 2 3 5 6 4 1 d clk q q pr cl u2 dff 1 2 3 q d clk r2 10 k u2 dff3 1 2 3 5 4 q d clk pr cl u? not 1 2 u2 nand2 1 2 3 u2 dff3 1 2 3 5 4 q d clk pr cl u2a 741 09 2 4 3 6 7 5 1 j clk k q q pr cl a1 4 clk rs- is- a0 a1 a2 r/w strb - dacv1 ds[0..15] l1 l2 l3 l4 sda t serck
MC3310 technical specifications 74 7.7 ram interface the following schemati c shows an interface circuit betw een the MC3310 and external ram. comments on schematic the cp is capable of directly addressing 32k wo rds of 16-bit memory. it will also use a 16 bit paging register to address up to 32k word pages. the schematic shows the paging and addressing for 128kb ram chips, i.e. 4 pages per ram chip. the page address d ecoding is shown for only 6 of the 16 possible paging bits. the decoding time from w/r and ds- to the memory output must not exceed 18 ns. for a read with no wait states. the writes provide 25 extra ns access time for w/r and ds- to reverse the cp data bus.
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a page register up to 16 bits note:the critical decode and memory access time is during read, the required access time is 18 ns. from ds- low. as illustrated there is ~ 100ns. to accomplish the decoding from page reg write to memory read or write. decoding will have to be carefully done on memories with a single chip select. note: pos139 is a standard 139 with inverted outputs b ram interface performance motion devices 55 old bedford rd lincoln, ma 01773 b 1 0 tuesday, november 19, 2002 title size document number rev date: sheet of vcc a0 a0 a1 d0 a1 d8 a2 d1 a2 d9 a3 d2 a3 d10 a4 d3 a4 d11 d0 mpg0 a5 d4 a5 d12 a0 d1 mpg1 a6 d5 a6 d13 a1 d2 cs1 a7 d6 a7 d14 d0 a2 d3 cs2 a8 d7 a8 d15 d1 a3 d4 cs3 a9 a9 d2 a4 d5 cs4 a10 a10 d3 a5 d6 a11 a11 d4 a6 d7 a12 a12 d5 a7 a13 a13 d6 a8 we - a14 a14 d7 a9 pgr- mpg0 mpg0 d8 a1 0 cs5 mpg1 mpg1 d9 a1 1 cs6 d10 a1 2 cs7 ds- ds- d11 a1 3 gnd cs8 cs1 cs1 d12 a1 4 d13 we- we- d14 w/r w/r d15 ds- d8 d9 d10 d11 we - d12 w/r d13 d14 d15 we - pgr- a0 a0 a1 d0 a1 d8 a2 d1 a2 d9 a3 d2 a3 d10 a13 a4 d3 a4 d11 is- pgr- a5 d4 a5 d12 r/w a6 d5 a6 d13 a7 d6 a7 d14 a8 d7 a8 d15 a9 a9 a10 a10 a11 a11 a12 a12 a13 a13 a14 a14 mpg0 mpg0 mpg1 mpg1 ds- ds- cs2 cs2 we- we- w/r w/r rs- clk d[0..15] a[0..14] d[0..15] a[0..14] vcc gnd is- r/w u2a pos1 39 2 3 1 4 5 6 7 a b g y0 y1 y2 y3 u2 74ls 377 3 4 7 8 13 14 17 18 11 1 2 5 6 9 12 15 16 19 d1 d2 d3 d4 d5 d6 d7 d8 clk g q1 q2 q3 q4 q5 q6 q7 q8 u2 74ls 377 3 4 7 8 13 14 17 18 11 1 2 5 6 9 12 15 16 19 d1 d2 d3 d4 d5 d6 d7 d8 clk g q1 q2 q3 q4 q5 q6 q7 q8 u? mc m6226 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 29 24 22 30 13 14 15 17 18 19 20 21 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 we oe ce1 ce2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u? mc m6226 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 29 24 22 30 13 14 15 17 18 19 20 21 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 we oe ce1 ce2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 r? 22 k u2 no t 1 2 u2b pos1 39 14 13 15 12 11 10 9 a b g y0 y1 y2 y3 u? mc m6226 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 29 24 22 30 13 14 15 17 18 19 20 21 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 we oe ce1 ce2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u? cp2n11 13 60 14 20 9 10 11 12 15 16 17 18 19 22 23 24 47 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 129 130 4 6 1 25 26 27 28 29 46 59 61 71 92 104 113 120 21 40 62 93 103 121 58 7 2 41 36 50 56 35 132 63 64 94 100 96 72 98 43 44 53 99 74 89 75 88 76 83 77 82 84 85 86 87 3 8 37 131 67 69 70 68 52 101 102 97 73 90 91 65 54 vcc vcc gnd gnd data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 vcc addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 ~ramslct ~periphslct r/~w ~strobe ~writeenbl data12 data13 data14 data15 gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc vcc clockin vcc vcc ~reset vcc vcc gnd ~rs w/~r poslim1 neglim1 axisout1 pwmmag1 pwmsign1 axisin1 ~hostintrpt srlrcv srlxmt i/ointrpt srlenable analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 analogvcc analogrefhigh analogreflow analoggnd gnd gnd gnd n/c quada1 ~index1 ~home1 quadb1 vcc pwmmag2 pwmmag3 pwmsign2 hall1a hall1b hall1c prlenable synch u2 or3 1 2 3 4 u? mc m6226 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 29 24 22 30 13 14 15 17 18 19 20 21 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 we oe ce1 ce2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7
MC3310 technical specifications 76 7.8 user-defined i/o the interface between the MC3310 chip and 16 bits of user output and 16 bits of user input is shown in the following figure. comments on schematic the schematic implements 1 word of user output registered in the 74ls377?s and 1 word of user inputs read via the 244?s. the schematic decodes the low 3 bits of the address to 8 possible uio addresses uio0 through uio7. registers an d buffers are shown for only uio0, but the implementation shown may be easily extended. th e lower 8 address bits may be decoded to provide up to 256 user output words and 256 user input words of 16 bits.
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a the logic labeled u2 may be implemented in a cpld. the lower 8 address bits, a0-a8, may be and 256 user outputs. decoded to provide 256 16 bit user inputs user inputs user outputs d user i/o performance motion devices 55 old bedford rd lincoln, ma 01773 b 1 0 tuesday, november 19, 2002 title size document number rev date: sheet of a0 uio0 a1 uio1 d0 uo0-0 a2 uio2 a0 d1 uo0-1 uio3 a1 d2 uo0-2 uio4 d0 a2 d3 uo0-3 uio uio5 d1 a3 d4 uo0-4 a3 uio6 d2 a4 d5 uo0-5 a4 uio7 d3 a5 d6 uo0-6 d4 a6 d7 uo0-7 d5 a7 d6 a8 we- d7 a9 uio0 d8 a1 0 d9 a1 1 d10 a1 2 d11 a1 3 d12 a1 4 d13 d14 d15 d8 uo0-8 a1 2 a12 n d9 uo0-9 uio d10 uo0-10 is- d11 uo0-11 we- d12 uo0-12 w/r d13 uo0-13 d14 uo0-14 d15 uo0-15 we- uio0 a12 n uion is- w/r ui0n uio0 d0 ui0-0 d1 ui0-1 d2 ui0-2 d3 ui0-3 d4 ui0-4 d5 ui0-5 d6 ui0-6 d7 ui0-7 d8 ui0-8 d9 ui0-9 d10 ui0-10 d11 ui0-11 d12 ui0-12 rs- d13 ui0-13 d14 ui0-14 clk d15 ui0-15 ui0n ui0n d[0..15] a[0..14] gnd vcc is- ui0n ui0n u2 or2 1 2 3 u2 or3 1 2 3 4 u2 24 4 2 4 6 8 11 13 15 17 1 19 18 16 14 12 9 7 5 3 1a1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 1g 2g 1y1 1y2 1y3 1y4 2y1 2y2 2y3 2y4 u2 13 8 1 2 3 6 4 5 15 14 13 12 11 10 9 7 a b c g1 g2a g2b y0 y1 y2 y3 y4 y5 y6 y7 r? 22 k u2 not 1 2 u2 nor2 1 2 3 u2 74ls 377 3 4 7 8 13 14 17 18 11 1 2 5 6 9 12 15 16 19 d1 d2 d3 d4 d5 d6 d7 d8 clk g q1 q2 q3 q4 q5 q6 q7 q8 u2 74ls 377 3 4 7 8 13 14 17 18 11 1 2 5 6 9 12 15 16 19 d1 d2 d3 d4 d5 d6 d7 d8 clk g q1 q2 q3 q4 q5 q6 q7 q8 u2 24 4 2 4 6 8 11 13 15 17 1 19 18 16 14 12 9 7 5 3 1a1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 1g 2g 1y1 1y2 1y3 1y4 2y1 2y2 2y3 2y4 u? cp2n11 13 60 14 20 9 10 11 12 15 16 17 18 19 22 23 24 47 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 129 130 4 6 1 25 26 27 28 29 46 59 61 71 92 104 113 120 21 40 62 93 103 121 58 7 2 41 36 50 56 35 132 63 64 94 100 96 72 98 43 44 53 99 74 89 75 88 76 83 77 82 84 85 86 87 3 8 37 131 67 69 70 68 52 101 102 97 73 90 91 65 54 vcc vcc gnd gnd data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 vcc addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 ~ramslct ~periphslct r/~w ~strobe ~writeenbl data12 data13 data14 data15 gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc vcc clockin vcc vcc ~reset vcc vcc gnd ~rs w/~r poslim1 neglim1 axisout1 pwmmag1 pwmsign1 axisin1 ~hostintrpt srlrcv srlxmt i/ointrpt srlenable analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 analogvcc analogrefhigh analogreflow analoggnd gnd gnd gnd n/c quada1 ~index1 ~home1 quadb1 vcc pwmmag2 pwmmag3 pwmsign2 hall1a hall1b hall1c prlenable synch
MC3310 technical specifications 78 7.9 12-bit a/d interface the following schematic shows a typical interface circuit be tween the MC3310 and a quad 12 bit 2?s complement a/d converter used as a position inpu t device. any single channel a/d can also be used provided it meets the interface timing requirements. comments on schematic the a/d converter samples the 2?s complement digi tal words. dacrd- is used to perform the read and is also used to load the counter to ffh. the counter will be reload ed for each read and will not count significantly between reads. the counter will therefore start counting down after the last read and will generate the cvt- pulse after 12.75 sec. the conversions will take approximately 35 sec, and the data will be available for the next set of reads after 50 sec. the 12 bit words from the a/d are extended to 16 bits with the 74ls244.
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a note:fs inputs are +- 10v dacrd- will load the counter to 255. 12.8 usec. after the last dacrd- the counter will reach 0 and start the next conversion. the input will be converted in 35 usec. ready for the next read 50 usec later. be implementedin a pld. note:the logic labeled u2 may note:sign extention for 2's complement a 12 bit a/d in performance motion devices 55 old bedford rd lincoln, ma 01773 b 1 0 tuesday, november 19, 2002 title size document number rev date: sheet of vcc pos 1 pos 2 pos 3 pos 4 cvt- dacrd- dacrd- a1 1 -5va cvt - encnt- clk clk dacrd- dacrd- encnt- dacrd- ds[0..15] vcc a2 ds7 ds4 ds8 ds1 a1 5 ds5 ds14 a1 3 a1 2 ds8 ds5 ds10 a1 0 ds3 gnd a1 1 ds3 ds15 strb - ds6 ds12 ds0 ds13 vcc agnd a9 a6 a0 ds10 ds1 a7 a1 ds4 w/r ds13 ds11 rs- a1 4 a3 ds9 gnd ds15 a8 ds0 ds6 ds11 ds7 a5 ds11 gnd ds[0..15] ds2 clk ds14 ds12 a4 ds9 ds2 a[0..15] clk is- vcc gnd u2 74al s169 3 4 5 6 2 9 1 10 7 14 13 12 11 15 a b c d clk load u/d ent enp qa qb qc qd rco u2 or4 1 2 3 4 5 u1 cp2n11 13 60 14 20 9 10 11 12 15 16 17 18 19 22 23 24 47 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 129 130 4 6 1 25 26 27 28 29 46 59 61 71 92 104 113 120 21 40 62 93 103 121 58 7 2 41 36 50 56 35 132 63 64 94 100 96 72 98 43 44 53 99 74 89 75 88 76 83 77 82 84 85 86 87 3 8 37 131 67 69 70 68 52 101 102 97 73 90 91 65 54 vcc vcc gnd gnd data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 vcc addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 ~ramslct ~periphslct r/~w ~strobe ~writeenbl data12 data13 data14 data15 gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc vcc clockin vcc vcc ~reset vcc vcc gnd ~rs w/~r poslim1 neglim1 axisout1 pwmmag1 pwmsign1 axisin1 ~hostintrpt srlrcv srlxmt i/ointrpt srlenable analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 analogvcc analogrefhigh analogreflow analoggnd gnd gnd gnd n/c quada1 ~index1 ~home1 quadb1 vcc pwmmag2 pwmmag3 pwmsign2 hall1a hall1b hall1c prlenable synch r? 22 k u2 74al s169 3 4 5 6 2 9 1 10 7 14 13 12 11 15 a b c d clk load u/d ent enp qa qb qc qd rco u2 not 1 2 u2 dff2 1 2 3 4 q d clk cl u2 not 1 2 u? ad7874 1 2 27 28 5 6 7 8 24 25 10 11 12 13 15 16 17 18 19 20 21 22 3 9 26 23 14 4 vin1 vin2 vin3 vin4 convst rd cs clk refin refout db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 vdd vdd vss agnd dgnd int u2 74ls 244 2 4 6 8 11 13 15 17 1 19 18 16 14 12 9 7 5 3 1a1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 1g 2g 1y1 1y2 1y3 1y4 2y1 2y2 2y3 2y4
MC3310 technical specifications 80 7.10 16-bit a/d input the interface between the MC3310 chip and a 16 bi t a/d converter as a parallel input position device is shown in the following figure. comments on schematic the schematic shows a 16 bit a/d used to provide pa rallel position input to axis 1 and axis 2. the expansion to the remaining two axes is easily implemented. the 374 registers are required on the output of the a/d converters to make the 68-nanosecond access time of the cp. the worst-case timing of the a/d?s specify 83 nanoseconds for data on the bus and 83 nanoseconds from data to tri-state on the bus. each time the data is read the 169 counter is set to 703 decimal. this provides a 35.2-microsecond delay before the next conversion. with a 10-microsecond conversion time the data will be available for the next set of reads afte r 50 microseconds. the delay is used to provide a position sample close to the actual position.
8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a note:fs inputs are +- 10v 38.4 usec. after the dacrd- the counter will reach 0 and start the next conversion. the input will be converted in 10 usec. ready for the next read after 50 usec. be implementedin a pld. note:the logic labeled u2 may dacrd- will load the counter to 700. see analog devices specifications for aditional information and power bypassing. a 16 bit a/d input performance motion devices 55 old bedford rd lincoln, ma 01773 b 1 1 tuesday, november 19, 2002 title size document number rev date: sheet of +5 a vcc a0 a1 ds0 a2 ds1 a3 ds2 a4 ds3 a5 ain1 ds4 a6 ds5 a7 ds6 a8 ds7 a9 ds8 a1 0 ds9 a1 1 ds10 a1 2 ds11 a1 3 ds12 a1 4 ds13 a1 5 cvt- ds14 ds15 gnd is- strb - dacrd- w/r a1 1n dacrd- gnd a1 1 a11 n agnd rs- clk gnd encnt- gnd clk clk clk dacrd- dacrd- dacrd- clk gnd gnd gnd encnt- dacrd- ds[0..15] ds[0..15] vcc vcc vcc cvt- a[0..15] vcc u2 74als 169 3 4 5 6 2 9 1 10 7 14 13 12 11 15 a b c d clk load u/d ent enp qa qb qc qd rco u2 or4 1 2 3 4 5 c1 2.2uf r2 33.2 u2 37 4 3 4 7 8 13 14 17 18 1 11 2 5 6 9 12 15 16 19 d0 d1 d2 d3 d4 d5 d6 d7 oc clk q0 q1 q2 q3 q4 q5 q6 q7 u1 cp2n11 13 60 14 20 9 10 11 12 15 16 17 18 19 22 23 24 47 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 129 130 4 6 1 25 26 27 28 29 46 59 61 71 92 104 113 120 21 40 62 93 103 121 58 7 2 41 36 50 56 35 132 63 64 94 100 96 72 98 43 44 53 99 74 89 75 88 76 83 77 82 84 85 86 87 3 8 37 131 67 69 70 68 52 101 102 97 73 90 91 65 54 vcc vcc gnd gnd data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 vcc addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 ~ramslct ~periphslct r/~w ~strobe ~writeenbl data12 data13 data14 data15 gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc vcc clockin vcc vcc ~reset vcc vcc gnd ~rs w/~r poslim1 neglim1 axisout1 pwmmag1 pwmsign1 axisin1 ~hostintrpt srlrcv srlxmt i/ointrpt srlenable analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 analogvcc analogrefhigh analogreflow analoggnd gnd gnd gnd n/c quada1 ~index1 ~home1 quadb1 vcc pwmmag2 pwmmag3 pwmsign2 hall1a hall1b hall1c prlenable synch u2 74als 169 3 4 5 6 2 9 1 10 7 14 13 12 11 15 a b c d clk load u/d ent enp qa qb qc qd rco r1 20 0 u3 ad976 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 2 5 14 28 27 26 1 3 4 25 24 23 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 agnd1 agnd2 dgnd vcc vana busy vin ref cap cs r/c byte c1 2.2uf u2 not 1 2 u2 37 4 3 4 7 8 13 14 17 18 1 11 2 5 6 9 12 15 16 19 d0 d1 d2 d3 d4 d5 d6 d7 oc clk q0 q1 q2 q3 q4 q5 q6 q7 u2 dff2 1 2 3 4 q d clk cl r? 22 k u2 not 1 2 u2 74al s169 3 4 5 6 2 9 1 10 7 14 13 12 11 15 a b c d clk load u/d ent enp qa qb qc qd rco
MC3310 technical specifications 82 7.11 external gating logic index a typical circuit for gating the index signal with the encoder a & b channels is shown in the following schematic. comments on schematic in order for proper operation of the index signal when used for position capture or phase correction, the signal must be gated with the a & b encoder channels to ensure that this signal is only active when all three signals are low. the motion processor does not perform this gating internally.
5 5 4 4 3 3 2 2 1 1 d d c c b b a a a external gating logic index performance motion devices 55 old bedford rd lincoln, ma 01773 b 1 1 tuesday, november 19, 2002 title size document number rev date: sheet of quada1 gnd vcc hom e1 indx1 index1 quadb1 quada1 quadb1 r? 22 k u3 or3 1 2 3 4 u1 cp24n11 13 60 14 20 9 10 11 12 15 16 17 18 19 22 23 24 47 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 129 130 4 6 1 25 26 27 28 29 46 59 61 71 92 104 113 120 21 40 62 93 103 121 58 7 2 41 36 50 56 35 132 63 64 94 100 96 72 98 43 44 53 99 74 89 75 88 76 83 77 82 84 85 86 87 3 8 37 131 67 69 70 68 52 101 102 97 73 90 91 65 54 vcc vcc gnd gnd data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 vcc addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 ~ramslct ~periphslct r/~w ~strobe ~writeenbl data12 data13 data14 data15 gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc vcc clockin vcc vcc ~reset vcc vcc gnd ~rs w/~r poslim1 neglim1 axisout1 pwmmag1 pwmsign1 axisin1 ~hostintrpt srlrcv srlxmt i/ointrpt srlenable analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 analogvcc analogrefhigh analogreflow analoggnd gnd gnd gnd n/c quada1 ~index1 ~home1 quadb1 vcc pwmmag2 pwmmag3 pwmsign2 hall1a hall1b hall1c prlenable synch

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